Yield improvement via automatic analysis of wafer-processing order

Miguel Alonso Merino; Miguel Recio; Julian Moreno; Victorino Martin Santamaria; Almudena Fernandez; Gerardo Gonzalez; Enrique Borrego; Luis J. Barrios; Maria D. del Castillo; Lissette Lemus; Angel L. Gonzalez

doi:10.1117/12.324372

28 August 1998 Yield improvement via automatic analysis of wafer-processing order

Miguel Alonso Merino, Miguel Recio, Julian Moreno, Victorino Martin Santamaria, Almudena Fernandez, Gerardo Gonzalez, Enrique Borrego, Luis J. Barrios, Maria D. del Castillo, Lissette Lemus, Angel L. Gonzalez

Author Affiliations +

Proceedings Volume 3510, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV; (1998) https://doi.org/10.1117/12.324372
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

Manufacturing tools may process wafers in different fashions: by group of lots, by lot, by group of wafers, one- by-one in single or multichamber tools,... The order sequence in which wafers are processed in a given step of the manufacturing routing can be used as a valuable source for yield improvement. Within this scope we published on SPIE's 1996 Microelectronic Manufacturing an Advanced Software System to correlate order-sequences versus any yield related metric. Since then we have developed a new generation of Software named POSISCAN which automates the analysis and detection of 'order patterns', that is, footprints of the yield being impacted by the order in which the wafers were processed in a specific tool. Yield degradation induced on each process can have a kind of footprint. We have accumulated a wealth of these footprints and developed a very fine knowledge-based algorithm to automatically detect them on every lot. The effectiveness of this automated POSISCAN tool is remarkably high and is having a big impact on time to detection/analysis/root-cause of yield loss.

Citation Download Citation

Miguel Alonso Merino, Miguel Recio, Julian Moreno, Victorino Martin Santamaria, Almudena Fernandez, Gerardo Gonzalez, Enrique Borrego, Luis J. Barrios, Maria D. del Castillo, Lissette Lemus, and Angel L. Gonzalez "Yield improvement via automatic analysis of wafer-processing order", Proc. SPIE 3510, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV, (28 August 1998); https://doi.org/10.1117/12.324372

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