Motion estimation and compensation optimization on IA32 CPU

Yihua Du; Chang Liu

doi:10.1117/12.574305

8 February 2005 Motion estimation and compensation optimization on IA32 CPU

Yihua Du, Chang Liu

Proceedings Volume 5637, Electronic Imaging and Multimedia Technology IV; (2005) https://doi.org/10.1117/12.574305
Event: Photonics Asia, 2004, Beijing, China

Abstract

Motion estimation (ME) and compensation (MC) is critical to the performance of an encoder, because the procedure is computationally intensive. To reduce the calculation, people work out some kinds of fast search algorithms for motion estimation, and dramatically improve the performance. This paper uses the Intel Pentium CPU's MMX, XMM registers and some Single Instruction Multiple Data (SIMD) instructions to accelerate the calculation, especially, uses PNI (Prescott New Instruction). We could load more pixels' values to a register at the same time. With PNI’s instruction LDDQU, we could load 16 bytes to XMM register even they cross a cache line boundary. Therefore, we could calculate (add, subtract, average, get absolute differences) multiple samples in a single operation. The parallel operations will significantly increase the speed of the ME and MC, irrespective of which kind of search algorithm.

Citation Download Citation

Yihua Du and Chang Liu "Motion estimation and compensation optimization on IA32 CPU", Proc. SPIE 5637, Electronic Imaging and Multimedia Technology IV, (8 February 2005); https://doi.org/10.1117/12.574305

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