A brief introduction of the purpose and organization of this seminar is given. In addition, papers in this seminar are indexed according to their approaches to the realization of real time signal processing to provide a bird's eye view of this diversified field.

Data management may be considered as the activity that organizes and communicates data, with data management systems delivering information and ultimately knowledge as end pro-ducts. For example, NASA/s Earth Resources Program has experimentally demonstrated that remotely sensed data from space can be processed and converted into scientifically useful information and knowledge that may provide solutions to the increasingly critical problems facing mankind. The data systems producing these important results perform complex func-tions sequenced to generate, process, and distribute data virtually on a problem-to-problem basis. It is not surprising that the demonstrated flexibility of data handling and process-ing does not provide the capability to handle the volume of data generated by modern sen-sors. This situation has manifested itself through very high costs of information and the long delays between the time the data are acquired and the time the desired information becomes available. Potential users have recognized the desirability of space-acquired in-formation, but they cannot afford it. This paper identifies the importance of satisfying both functional and economic considerations. It shows that the issue of affordability associated with information systems can be predicted prior to actual system implementation. These requirements have indicated that future information systems must deliver substantially larger volumes of information at significantly reduced costs. Advanced technology-inspired approaches can provide real-time data management systems. This alternative solution has the potential for increasing information availability by a factor of 1000 and reducing the costs proportionally.

The spacecraft synthetic aperture radar (SAR) data processing functions required to produce real-time imagery can be accomplished by time domain correlation in the range and azimuth dimensions. Charge-coupled device (CCD) large-scale integration (LSI) technology may be used to implement range and azimuth correlators that are practical for future on-board applications. An already demonstrated N-stage CCD LSI transversal filter chip, providing N signal-by-weighting coefficient multiplications each clock period, offers a poten-tially attractive basis for achieving the range correlation function. Furthermore, a custom CCD LSI azimuth filter chip, currently under development by the Caltech Jet Propulsion Laboratory (JPL), provides a potentially practical means for individually performing all of the necessary parametric corrections and correlation functions to produce complete image lines from range correlated data. By using M such azimuth filter chips in parallel, corres-ponding to the number of pulses coherently integrated in azimuth, a real-time processing capability can be achieved. This paper describes (1) applicable SAR processing principles, (2) typical requirements associated with real-time SAR processing, and (3) a real-time on-board SAR processing implementation approach using the aforementioned CCD techniques for achieving the range and azimuth correlation functions.

Given specific system performance requirements and flexible subsystem boundaries, the means of implementing target sensor signal processing functions in today' s device technologies becomes a multi-choice problem. This paper presents the results of recent studies to determine the attributes and draw-backs of mechanizing missile radar signal processing functions in various candidate device technologies. Using a Schottky-bipolar-based design as a point of departure, alternative, complementary metal-oxide semiconductor, analog and digital charge-coupled-device designs were configured and evaluated. The dynamic nature of the sensor in its repetitive and cyclic acquisition of new data, together with the interface, computing precision and delay, flexibility, low power and small volume design constraints of missile systems, were significant screening factors in the evaluation process.

One of the primary problems encountered by a field commander is the timely location and engagement of battlefield targets. In recent years, tremendous advances have been made in gathering and processing photogrammetric data which is being used to develop data bases covering major potential battlefield areas. Through technology developed by the U.S. Army Engineer Topographic Laboratories (USAETL), Fort Belvoir, Virginia, the potential of a new technique for positioning targets detected in the battlefield within minutes after obser-vation has been demonstrated. A brassboard system for tactical positioning was fabricated at USAETL using an Optical Area Correlator (OAC) developed by Boeing under contract with the Air Force. The OAC uses incident light and is capable of correlating real-world imagery with data-base photography. The output signals from the OAC are scene signatures containing less than 400 bits of information. This paper will describe the brassboard hardware and the test results obtained from the OAC when (a) correlating between aerial stereo photographs, (b) correlating real-world signatures obtained at 6, 8, and 10 thousand feet with data-base photographs, and (c) correlating signatures between a 32 feet by 32 feet, 1/600 scale, three-dimensional terrain model located at Redstone Arsenal, Alabama, and a photographic mosaic of this same model.

Underwater Acoustic Imaging is the use of high frequency sound to derive images of objects underwater, usually on the ocean floor. Used to augment optical imaging techniques when optical visibility is too short, acoustic imaging must still provide timely (i.e. real time) information with respect to the actions it can affect. At present, much of the signal processing for underwater acoustic imaging is performed electronically in either analog or analog and digital forms. It involves primarily Fourier transforms and smoothing algorithms at present. Further signal processing in this area should be faster, and should encompass more operations, including image enhancement and 3-dimensional display processing. It is also possible that analysis of the time structure of the acoustic echo can provide information on texture, composition or other qualities of the object for display as color, although this area is still being researched. In short, underwater acoustic imaging is a promising field in need of significant amounts of real time signal processing to make it practical.

This paper is a survey and tutorial of high-performance parallel processors. It covers the subjects of multiprocessors, pipeline processors, array/associative processors and scientific processors. Architecture summaries are provided.

In this review paper a summary of the research progress on wideband integrated (guided-wave) optic signal processors which was made most recently at the authors' institution is described. The three devices that have been examined are: (1) High-Speed Acoustooptic Readout Device for Integrated Optic RF Signal Processing*, (2) High-Capacity Time-Integrating Acoustooptic Correlator**, and (3) High-Speed Electrooptical Analog-to-Digital Converter.

Modem signal processing frequently requires linear transforms in both space and time, such as beamforming and temporal Fourier analysis. Such linear processing operations form a large portion of the computational load for many signal processing problems. Convolu-tional devices including transversal filters and crossconvolvers form highly parallel computations modules with high throughput and minimal control overhead. Such modules may be used not only for time-invariant linear transforms such as matched filtering and cross-convolution, but also a large class of time-variant linear transforms such as one-dimensional and two-dimensional Fourier transforms and beamformers for selected array geometries, including one-dimensional and multidimensional uniformly spaced arrays, the circular array, the power law curve array, and the exponentially spaced line array. Special architectures using uniformly tapped multiport (program-mable) convolvers are applicable to a wider set of array geometries the generalized Lissajous figure arrays. In several cases, the same architecture will accommodate a variety of array geometries by simply changing the output of a function generator. To extend these techniques to a completely arbitrary, time-varying array requires the equivalent of a multiport convolver with moveable taps. The most attractive candidate for such a device at present is a further development of the acousto-optic memory convolver.

Special purpose hardware implementation of DFT Computers and digital filters is considered in the light of newly introduced algorithms and IC devices. Recent work by Winograd on high-speed convolution techniques for computing short length DFT's, has motivated the development of more efficient algorithms, compared to the FFT, for evaluating the transform of longer sequences. Among these, prime factor algorithms appear suitable for special purpose hardware implementations. Architectural considerations in designing DFT computers based on these algorithms are discussed. With the availability of monolithic multiplier-accumulators, a direct imple-mentation of IIR and FIR filters, using random access memories in place of shift registers, appears attractive. The memory addressing scheme involved in such implementations is discussed. A simple counter set-up to address the data memory in the realization of FIR filters is also described. The combination of a set of simple filters (weighting network) and a DFT computer is shown to realize a bank of uniform bandpass filters. The usefulness of this concept in arriving at a modular design for a million channel spectrum analyzer, based on microprocessors, is discussed.

A proposed architecture for real-time signal processing is discussed. The architecture consists of 2n microcomputers connected through a switching network that makes the entire array into what we call the "indirect binary n-cube array." By a microcomputer we mean a microprocessor together with memory, some of which can be read-only or write-occasionally. The microcomputers are operated in lockstep under broadcast macroinstructions from a central controller which can also be a microcomputer. The macroinstructions are locally interpreted in a programmable way as a sequence of microinstructions. The central controller also manages the switching array, as well as handling I/O to and from the array. It is shown that this design can make full use of the 2n-fold parallelism for most signal processing algorithms including, for example, the radix-2 FFT in one or two dimensions, windowing, doppler filtering, and the like. Furthermore, the design is such that the array, and hence the available degree of parallelism, can be halved or doubled without requiring redesign; it can therefore be adapted to changing requirements.

The incremental cost per unit of performance of a variety of flexible system functions has been sharply reduced through the application of a high degree of functional parallelism with serialized arithmetic. (Functional parallelism as used here is the parallel use of an array of high density, low cost, lower performance devices to obtain a high performance function.) System functions, such as fast Fourier transformers, digital filters, graphics function generators, and matrix computational arrays have all been reduced to a form which is highly channelized in this manner. Such computationally intensive digital signal processors employing novel computational means are shown to promise a reduction in size, weight, and power by an order of magnitude over conventional techniques. Several examples of modular functional processors are presented for which the algorithmic formulation, architectural configuration, and prototype implementation are described.

The exact definition of floating point computation has always varied from one computer to another and from one implementation to another. However, three points are common to almost all systems in use today: 1) representation of numbers by a multiplier and an exponent, with fixed integer base, 2) restriction of multiplier magnitude range (l/b,l) for uniqueness, 3) unique representation of zero. To implement the four operations, addition, subtraction, multiplication and division, for floating point, whether in hardware or in software, a worst case time can be identified which, for addition and subtraction, is often much larger than the average expected execution time, and which must be provided for in a real time system. An examination of the loss in accuracy associated with approximations which reduce these worst case times has led to a re-examination of an old idea, unnormalized floating point arithmetic, in the light of availability of modern hardware. We find that a system something like unnormalized floating point arithmetic is just right for most signal processing applications.

In digital signal processing a great majority of repetitive operations are arithmetic in the form of sum of products. Specialized parallel arithmetic hardware such as multiplier, multiple argument adder, etc. are being developed for this application. With the availability of multivalued logic gates , it becomes feasible to implement non-binary arithmetic which leads to denser hardware. Theoretical bounds on the complexity in non-binary arithmetic are compared to binary ones. A brief description of the quaternary I²L family precedes design examples of arithmetic operators in radix 4. Single component complex arithmetic operations in balanced base 3 are mentioned. Operators in GF (4) and in the extension fields are also shown, as possible tools in number theoretic transforms N. T. T.

A number of on-line signal processing algorithms are being proposed for digital image processing. Some of these require recursive iterations in the arithmetic computations. For example, 2-D recursive filters are being used to transform and/or filter digital images in microprocessors. Inherent to microprocessors is the extremely short wordlength (8-16 bits) and, as a result, arithmetic operations are no longer precise and "C" noise is evident. These machines are being further proposed for adaptive filtering operations which aggravates the truncation/rounding effects since computations are now nested and errors are no longer statistically independent. In this paper the effects of truncation/rounding are depicted in the above setting by simulation examples.

Many real-time signal-processing applications found in image-processing fields require high computational throughput rate and serial. data storage capacity. Digital charge-coupled device CCD)( memories offer a potential solution to many of these applications. This paper discusses the major features that make CCDs attractive for high-volume serial storage requirements. 'Texas Instruments 64K CCD memory is described as an example to highlight architectural considerations and design tradeoffs. Projections for CCD memories are given with regard to cell structure and size, limits of packaging density, Inemory size, performance, and cost. Several digital CCD memory efforts in image processing are discussed and reviewed.

SOS technology has definitely come of age. It offers many advantages, it is easy and economical to use, and it has proven performance in a wide range of real-time signal processing applications. The principal advantages of SOS LSI, as far as the designer of real-time systems is con-cerned, are high speed and low power requirement. Often of equal advantage is high device density. These and other advantages are listed in Table 1 along with characteristics that make them possible. Several comparative disadvantages of using SOS have been cited in the past. Most of these have been alleviated, as indicated by the up-to-date evaluations in Table 2.Table 1. What SOS Offers the System Designer_ Advantage T Contributing Factor Low Dynamic. Power Small geometry devices with minimum device capacitance. High Density Elimination of guard bands Wide Range of Complementary Operating Voltages structure. Radiation Resistance Elimination of latch-up and high peak photocurrent. Simplified Design Exotic clocking systems not needed for high-speed static logic. Easy to Model Device performance can be reliably simulated using known dimensions and standard material constants.Table 2. An Update on Historical Disadvantages of SOS Disadvanges Current Evaluation Lack of Advantage) High Cost of Material Cost reduced to com-petitive level by 3-inch wafers and ribbon sapphire. High Densities in Bipolar circuits, Other Technologies dynamic NMOS-memories, and ILL are more dense -- but the power requirement is 4 to 10 times high than for SOS. Low Power Can be, At a trade-off for Achieved for ILL performance. High Speed Can be True, with the large Achieved with choice of components Other Technologies in bulk MOS and bipolar.The basic technologist can argue many more pros and cons for any technology. The systems designer must be cognizant of these pros and cons, but he has to extend his viewpoint to implementation and economics. He wants to design and partition systems in a cost-effective manner. Beyond the SOS combination of power, speed and density advantage are two major implementation assets -- the ready availability of powerful CMOS/SOS microprocessors and memories, and design methods utilizing an array of computer-aided design tools that quickly make concepts realizable in LSI and VLSI arrays. In the following pages, we briefly review three design methods, starting with handcrafted custom design -- which does incorporate some computer aids -- and proceeding to the highly automated standard cell and universal gate array approaches. Then, we get to the proof of the pudding -- descriptions of a range of applications in which SOS circuits and microproc-essors have been central to innovation and success. We end with an indication of progress in SOS technology that the designer of real-time systems will have at his disposal in the next few years.

A new byte organized LSI ECL shared resource programmable radar signal processor is being developed. Processor architecture, software, partitioning and physical design are described and benchmark performance data are projected.

The CMOS/SOS Microsignal Processor (µSP) is a 12-bit general purpose programmable, pipelined signal processor designed to efficiently perform digital filtering and processing algorithms. The architecture of the µSP is built of three elements - control, arithmetics, and memory: control consists of a sequencer and address generator; arithmetics consist of a scaler/shifter, 12 x 12 multiplier, a dual ALU and multipart memories; and Data memory consists of commercial 4K memory chips. Programmability is achieved through a stored program which calls and implements desired micro instructions in the arithmetic pipeline. A typical µSP can be programmed to implement various length complex or real FFTs, perform correlation/convolution, and sundry vector operations and digital filtering tasks. For example, the three architecture elements - control, memory and arithmetics operate in parallel to per-form a 1024 pt complex FFT in 3 ms (memory to memory). A typical CMOS/SOS µSP is designed for single chip carriers grouped into six hybrid types and fit onto one two-sided 6 in. by 9 in. module. The µSP is designed to be T2L interface compatible and operate at 10 V with 30-35 W of power dissipation. This paper will present the background leading to the design, describe the architecture and discuss the CMOS/SOS chips involved in the design.

An Optical Parallel Logic (OPAL) device which performs Boolean algebraic operations on binary images has been developed. This device consists of a photoconductor and an electro-optic light modulating material appropriately arranged to bring about an interaction between the input signals. Two such OPAL devices have been interconnected to form a half-adder circuit which is one of the essential components of the CPU in a futuristic digital optical processor. Operation of an 8 x 8 OPAL device containing CdS (photoconductor) and twisted nematic liquid crystal (electrooptic light modulating material) was demonstrated. A contrast ratio of 20:1 was obtained. A circuit composed of two such devices was shown to perform addition of two 8 x 8 binary images generating SUM and CARRY images.

Recent improvements in broadband, large time-bandwidth product surface acoustic wave (SAW) chirp filters have led to significant advances in the implementation of the Chirp Transform algorithm for analog signal processing. This paper concentrates on real-time Fourier transformation techniques for performing broadband spectral analysis and correlation using SAW chirp transformation. First, the fundamentals of the SAW chirp filter and the Chirp Transform algorithm are reviewed. Next, chirp transform system architectures are discussed, including the relationship between SAW filter de-sign and signal processor bandwidth, resolution and signal to noise ratio. Performance data is then presented for a new radar pulse-compression processor* which utilizes the Chirp Transform and incorporates state-of-the-art SAW chirp filters to perform cross-correlation between large time-bandwidth product waveforms. This "programmable" correlator is compatible with arbitrarily coded signals up to 60 psec long, with up to 60 MHz bandwidth. Finally, the SAW chirp transform is compared with other techniques for performing Fourier transformation, and specific applications of this technology for spectral analysis and correlation are discussed.

MIT Lincoln Laboratory is perfecting surface-acoustic-wave, acoustoelectric and charge-coupled devices which perform the functions of correlation and Fourier transformation and meet the requirements for radar and communication systems. Examples will be given of the performance limitations of acoustoelectric convolvers and memory-correlators, of chirp-transform devices, and of programmable CCD matched filters. A critical evaluation of the suitability of these components for system applications will be given.

Acousto-optic devices have been developed for implementing advanced signal processing functions required for real-time and near-real-time analysis of both high-frequency radar signals and low-frequency sonar signals. These devices use the Bragg interaction between laser beams and surface acoustic waves (SAW'S) to perform waveform convolution and correlation, achieving time-bandwidth products of 3000 to 10,000 with dynamic bandwidths of several hundred megahertz. Using these devices, wideband (about 100 MHz) signals have been extract-ed from extremely noisy environments (-30 dB signal-to-noise ratio) and a real-time Fourier transformation with a linear dynamic range exceeding 50 dB has been performed. A programmable correlator and a programmable filter have been demonstrated that use the newly discovered acousto-photorefractive memory effect. This effect is based on a nonlinear interaction between intense, short-duration laser pulses and a SAW signal propagating in lithium niobate, to form a semipermanent index-of-refraction pattern corresponding to the SAW signal. An implementation of the triple-product convolver architecture (proposed by Whitehouse et al.) for performing either a long one-dimensional or a two-dimensional discrete Fourier transform can be obtained by combining an acousto-optic convolver with many CCD chirp-Z transform modules. This triple-product convolver would have extremely rapid data handling capability and large dynamic range, and would be useful for applications such as "co-k" beam-forming for sonar signal processing. Further, a programmable 1-, 2-, 3-dimensional beam-former with a one second update capability may be feasible if the acousto-photorefractive memory effect is used to store SAW signals corresponding to the position of nonstationary sensors.

Over the past few years there has been an exponential increase in interest in analog processing technology. This is largely due to economics. The cost of digital processing at very high data rates is often prohibitive. In addition, many of the components required for optical processing have matured to the "off-the-shelf" stage. A significant portion of the effort in optical processing has shifted from components development to processing architecture. The time integration architecture offers the following advantages: a. It makes the most effective use of CCD arrays as sensors. b. It often produces a significant data rate reduction. (output rate is often orders cf magnitude below the input rate) c. It does not require a two dimensional electrooptic modulator to implement two dimensional operations. The following paper reviews past efforts in one dimensional time integrating processors and introduces the two dimensional time integrating correlator. This correlator can implement a variety of operations including ambiguity functions and large time bandwidth spectrum analysis (two dimensional).

It is often convenient to transmit video signals over a data channel. However, when a signal is digitally encoded using PCM, the data rate is extremely high. For example, using a 4MHz bandlimited video signal, the data rate is often 48-64 Mbs. Further, typical film based image sensors generate billions of bits of information which take a long time to convey over realistic data channels. Thus in applications where real-time image transmission is of interest there is a need to compress the analog video bandwidth. In this paper we report on experiments that use hybrid source encoding techniques to compress video images. We use analog coherent spatial Fourier filtering for preprocessing and real-time linear and adaptive video delta modulators to digitally encode video images. The effects of spatial filter and digital rate parameters on image bandwidth compression is determined. Results of amplitude companding using half-tone techniques are also considered.

A coherent optical method capable of performing arbitrary two-dimensional linear transformations has recently been studied, in which transform coefficients are given by two-dimensional inner products of the input image and a set of basis functions. Since the inner product of two functions is equal to the value of their correlation when there is zero shift between the functions, it is possible to use an optical correlator to solve for the coefficients of the transform. By using random phase masks in the input and the filter planes of the correlator, we have been able to pack many coefficients close together in the output plane, and thus take better advantage of the space-bandwidth product of the optical system. Both the input random phase mask and the spatial filter are computer-generated holographic elements, created by a computer-controlled laser beam scanner. The system can be "programmed" to perform arbitrary two-dimensional linear transformations. For demonstration, the set of two-dimensional Walsh functions was chosen as a transform basis. When the resolution of the Walsh functions was limited to 128 x 128, up to 256 transform coefficients were obtained in parallel. The signal-to-noise and accuracy of the transform coefficients were compared to the theory.

A 128-stage CCD analog correlator was fabricated which demonstrates several important features including: -- Correlation accuracy from input-to-input better than 0.2%. -- Overall correlation nonlinearity < 1%. -- Dynamic range = 105 dB√HZ. -- Complete 128-stage correlator fabricated in 200 x 50 mil chip.

This paper describes the investigations of various techniques employed to compensate the degradation in the modulation transfer function as a direct consequence of charge-transfer inefficiency in charge-transfer device applications where the inefficiency cannot be neglected, then describes these techniques in applications using CCD delay lines and imaging arrays.