The performance of W-Ti alloy as an x-ray mask absorber material was investigated in order to obtain a low distortion x-ray mask. The W-Ti films were deposited by sputtering the W-Ti (1wt% Ti content) target using Ar + N2 gas with a DC magnetron sputtering system. It was found that the internal stress and the density in the W-Ti films strongly depend on the gas pressure and N2 content of the Ar + N2 sputtering gas. The internal stress of W-Ti films deposited using Ar + N2 of 30% N2 content decreased with increasing gas pressure from a very large compressive stress, and became small in the region of above 2 Pa. The stress in W-Ti films deposited in this pressure region was very small (0.5-2.0 x 107 N/m2). This value is fully satisfactory for an x-ray mask absorber. The density of the low-stress W-Ti film is also satisfactory for the x-ray mask absorber. The etching properties of W-Ti film were evaluated for CF4 + 02 gas plasma. It was found that the etching rate becomes the maximum (1500 Å/min.) at the 02 content of 15-20%. In order to demonstrate the accuracy of the W-Ti x-ray mask, the full exposure mask (BN/Polyimide membrane) and the stepper mask (SiN/Polyimide membrane) were fabricated. As a result, x-ray masks with very small distortion (less than 0.1pm for 15 x 15mm field ) were obtained. It is concluded that the low distortion W-Ti mask is practical for use in submicron VLSI fabrication.

SiC-Au-stepper masks have been used for the fabrication of sub-micron devices by SOR based X-ray lithography in connection with a high precision alignment. As a test device we chosed a sub-micron transistor with four lithographic layers. The gatelength and the gate-width is scaled down from 2.0 pa to 0.5 wri, and 8.0 p.m to 1.0 p.m respectively. The SiC-mask blanks have been fabricated in a batch process by high temperature CVD deposition. Due to extensive process optimization SiC-membranes with a very smootA surface (RMS-roughness < 20 nm) and a Young's modulus as high as the bulk value (4.6•19 Pa) have been fabricated. Membranes of 2.5 4m in thickness having areas of up to 28 cm are being prepared with excellent transparency for synchrotron and optical radiation. For high X-ray absorption electroplated Au absorbing pattern have been applied. The combination of rigid SiC-membranes with a stress reduced Au-absorber (stress less than 1•10 Pa) will result in a mask distortion of less than 5 ppm even for a "worstcase" geometry of membrane and absorber pattern. Precise 0.5-micron pattern with an excellent control of the critical dimensions have been generated by e-beam lithography and electroplating, as well as mask copying by using synchrotron orbit radiation (SOR). Due to the excellent detection accuracy of the alignment pattern in case of SiC-masks (6 nm) a practical determined alignment accuracy of 40 nm has been obtained by using the MAX1 stepper at BESSY.

X-ray mask fabrication based on BCN compound membrane and gold containing polymeric carbon ( Au-C ) absorber by totally dry processes is proposed. The Au-C films were depo-sited by plasma polymerization of propylene or styrene monomers and co-evaporation of gold. These films have 2 to 5 times higher etching rate than that of pure gold for 09 RIE, depending on the Au content. The stress in the films could be reduced to 1.9 E 7 N/m2 by annealing. The BCN films were deposited on silicon wafers by rf (13.56 MHz) plasma CVD with diborane, methane and nitrogen as source gases at typical deposition rate of 30 nm/min. The optical (633nm) and X ray (Pd L∝) transparencies were nearly 80% for film thickness of 6 um. Patterning of Au-C was achieved by using tungsten as intermediate layer and PMMA electron beam resist. CF4 RIE was used to etch the tungsten layer which in turn acted as mask for the gold carbide 02 RIE. The process parameters and the characteristics of the Au-C and BCN films are presented.

Laser produced plasmas are investigated both theoretically and experimentally with respect to their suitability as X-ray lithography sources. We find that a minimum of 100 W average laser power is required for an acceptable wafer throughput (36 6 in. wafer/h). In addition, the optimization of the X-ray conversion efficiency in the keV range (0.75-2 keV) necessitates a laser intensity greater than 1 x 1013 W cm^-2 and a judicious choice of target atomic number. We also describe a simulation program called XLIMLAS which can be used, for instance, to determine the laser conditions which maximize the energy deposited in the resist by matching the X-ray spectrum to the wavelength dependent mask substrate transmission and to the resist absorption. Moreover, this optimisation must ensure a high quality of the resist line edge profiles. Finally, we present some experimental results on sensitivity and patternability of FBM120 resist.

A broadly applicable lithography tool figure of merit will be presented and evaluated for present technologies. A comparison of the cost effectiveness of current lithographic technologies shows that a laser generated, soft x-ray plasma proximity stepper is superior to competing technologies for production applications at one micrometer and below. The technology developments that make a soft x-ray proximity stepper more cost effective than other high resolution lithographic technologies will be discussed. Soft x-ray exposure sensitivity data will be presented for conventional novolak resists and acid catalyzed high sensitivity novolak-based materials. Resist profiles from soft x-ray exposures of standard, novolak-based resists will be compared to simulations obtained from a modified version of SAMPLE. In addition, x-ray and optical aerial image contrast calculations from SAMPLE will be compared. Novel aspects of the patented, high brightness Hampshire x-ray source will be presented and a comparison to other x-ray sources will be made. Lastly, the preliminary performance of a stepper employing Hampshire's laser-based x-ray plasma source will be presented indicating the performance achieved to date.

The compact synchrotron-radiation (SR) source is being developed for industrial use, especially for X-ray lithography. This source named AURORA, consists of a 150-MeV microtron injector, a 650-MeV superconduct-ing electron storage ring, and SR light channels. The injector is a pulsed racetrack microtron, which is 1.1-m width, 3.7-m length, and 1.5-m height. The storage ring is a superconducting weak-focusing single-magnet machine of 1-m orbital diameter, having an outside diameter of 3 m and a height of 2.2 m. The source size is uniform throughout the circumference, ar=1.4 mm in the radial direction, and σz= 0.2 mm in the vertical direc-tion. The critical wavelength is 1.0 nm. The irradiative power is 1.5 W/mrad at a stored electron current of 300 mA. It is anticipated that the lifetime of the beam will exceed 24 hours. Sixteen outlets are available for SR emission from the ring. Prototype machines are presently under construction. The present status and details of the machines will be reported in a later section of this paper.

This paper describes the replication and transfer of half-μm patterns into poly-Si and aluminum layers by means of x-ray lithography with synchrotron radiation and subsequent dry etching. The results show that plasma etching in a parallel plate reactor with powered upper electrode, working in the high pressure region is capable of anisotropic replication of half-μm features. Two novolak-based x-ray sensitive resists, Hunt HPR 204 and Hunt WX 242, were used as an etch mask. The processes employed were CC1⁴/He and C1₂/BC1J/CC14/N2 recipes for structuring poly-Si and aluminum respectively. The optimization of the Al etch recipe showed that the linewidth loss can be reduced below 0.05 pm by proper adjustment of the nitrogen flow.

An energy-dependent soft x-ray-induced device damage has been discovered in MOS devices fabricated using standard CMOS process. MOS devices were irradiated by monochromatic x-rays in energy range just above and below the silicon K-edge (1.84 keV). Photons below the K-edge is found to create more damage in the oxide and oxide/silicon interface than photons above the K-edge. This energy-dependent damage effect is believed to be due to charge traps generated during device fabrication. It is found that data for both n- and p-type devices lie along a universal curve if normalized threshold voltage shifts are plotted against absorbed dose in the oxide. The threshold voltage shift saturates when the absorbed dose in the oxide exceeds 1.4X105 mJ/cm3, corresponding to 6 Mrad in the oxide. Using isochronal anneals, the trapped charge damage is found to recover with an activation energy of 0.38 eV. A discrete radiation-induced damage state appears in the low frequency C-V curve in a temperature range from 1750C to 325°C.

The features of the ion-solid interaction most often used in microfabrication are implantation, sputtering (ion milling), and induced chemical reaction. The novelty of focused ion beam fabrication is that most of these processes can now be carried out with better than 0.1 μm resolution without the use of mask or resist. For implantation the species available include the dopants of Si and GaAs (such as B, As, Be, and Si). Energies up to 300 keV are achieved if doubly ionized species are used. The focused ion beam systems can deliver a desired dose with 0.1 μm accuracy aligned to existing features on the wafer. So far, a number of applications of this unique maskless resistless patterning capability have been reported, including: threshold adjust of transistors, transistors fabricated with graded doping profiles and tunable Gunn diodes. In addition, focused ion beams promise to be competitive with e-beams for pattern writing in resist.

For practical use of focused-ion-beam technology in the advanced-device fabrication, an alignment technique between an ion beam and a wafer is quite important because it restricts the overlay accuracy of patterns on a substrate. Secondary electrons generated by the ion beam irradiation are detected as a signal for registration. The detector is micro-channel-plate, which has an advantage that detected signal is not affected by the geometrical arrangement of registration marks. The marks and ion beams for the experiments are Au pedestals on the GaAs substrate, and 192keV Be++ and 260keV Si++, respectively. This type of mark can be fabricated as the same process step with the source and drain electrodes of GaAs microwave devices. The detection accuracy of the mark is defined as the distribution (3a) of the measured mark locations for a number of beam scans. The detection accuracy of 0.02μm or less for both ion beams was obtained by suppressing the effect of mark edge roughness using the data averaging of detected edge positions. The overlay accuracy, especially overlay repeatability (3a), were 0.11μm for Be⁺⁺ and 0.13,μm for Si⁺⁺. These suggested that this alignment technique is available for mushroom-shaped gate fabrication by a mixed exposure of Be++ and Si⁺⁺. A GaAs MESFET for microwave applications has been fabricated by the direct-writing process using the mixed exposure of these ion species.

Focused-ion-beam (FIB) microcircuit modification is a maturing technology which provides an accurate method of modifying the metal levels of an in-process or completed integrated circuit. New FIB processes are being developed which facilitate submicrometer conductor disconnects and conductor creation. We present a description of the key elements of an FIB system designed for this application and provide results of the machine's operation.

Low energy FIB less than 1 keV is useful for shallow doping or gas-assisted etching without damage to the substrate. An optical system with a retarding field has the ability to focuse an ion beam of low energy into a spot less than 0.1 μm in diameter. An improved type of the retarding mode optical system with a retarding electrode was designed, and some optical property calculations were achieved for this system. A retarding electrode above the specimen surface enables SE detection, but it worsens the focusing properties. Better focusing conditions are found by introducing a condenser lens to this system.

The application of thin semiconductor layers as etch masks for high vacuum lithography is described. Heteroepitaxial layers of In0.53 Ga0.47 As or InP, as thin as 30Å, were grown by molecular beam epitaxy and patterned using a focused beam of Ga ions. The patterned thin layer is then used as a mask for deep, material selective etching. This combination of molecular beam epitaxy and efficient precise patterning techniques is expected to result in a new flexibility in design and fabrication of semiconductor devices.

The focused ion beam (FIB) process has been examined for device production with an optical stepper. The FIB system developed performs and alignment procedure with a precise controlled stage. The registration accuracy attained by FIB lithography using Be and Si ions with the same or different ion energies showed good values with alignment marks covered with resists. The hybrid process with fine pattern delineation depending on FIB and with high throughput depending on an optical stepper indicated a promising tool for submicron devices.

Focused ion beam (FIB) repair of opaque defects on photomasks, generally utilizes ion beam induced sputter etching. Surfaces which have been etched by this method sometimes suffer from a loss of transmissivity for several reasons. Among these are, incomplete removal of the chrome film, damage to the substrate from overetching, and implantation of gallium. In the lithography process, any one of these can result in printing of the repaired areas. In an effort to improve the transmissivity of etched areas, post-repair processes such as wet chemical or plasma etching of the substrate have been utilized. These types of processes demonstrate major disadvantages because of the change in reflectivity brought about by the etching action over the entire substrate surface, as well as the addition of another process step, which significantly reduces overall repair throughput. Seiko has developed a proprietary (patents pending) method of sputter etching opaque defects using FIB, resulting in opaque defect repair areas with greater than 97% trans-missivity and significantly reduced gallium concentration levels; without the need for any additional post-repair processing. This paper will present the results of lithography tests and auger anlayses that were conducted to compare our current technique of opaque defect repair with the new technique.

A two lens, 25 keV electrostatic ion gun has been constructed which uses a liquid metal ion source and which is capable of high resolution (50 nanometers) and high current density in the focused spot (J > 3 A/cm2) at reasonable working distances (25 mm). Variable current is achieved by using a variable aperture between the lenses. The high performance is a result of optimizing the state of focus for the lenses for each aperture angle. The effect of a beam crossover between the lenses has been calculated and a crossover system performance is compared with collimated and optimized systems. While the best performance can be achieved by optimization, good performance can be achieved with a crossover if the crossover position is properly chosen.

Frequently occurring questions such as the minimum dose necessary to expose a resist system in electron beam lithography were investigated to determine the limits of resist performance at half micron dimensions and below. The processing window for exposing and developing resist coated wafers is presented as a function of the development conditions. Optimum exposure and processing conditions will be defined as these parameters relate to resist contrast. Several methods for fine tuning a resist process for electron beam lithography at 0.54um dimensions and below are presented. Various techniques are discussed which are used as variables to achieve the line width control necessary for multilevel lithography at ground rules of +0.1µm 3a for 0.5μm fully scaled devices and circuits. In addition, the intimate relationship of the resist contrast and sensitivity to the trade-offs of resist processing are also discussed.

Novolac reists have been widely used in microlithography due to their high resolution, thermal stability and dry etch resistance. One such resist, Shipley MP 2400, is used for both e-beam and deep UV lithography. In this paper, using e-beam lithography, we explore the effect of resist development parameters upon MP 2400 contrast and resolution. In particular, it is observed that resist contrast is strongly dependent on both developer dilution and developer temperature. Our experiments were performed using an immersion development system with a laser endpoint detector. This system facilitates controlled experiments since resist dissolution can be monitored directly during development. Another consideration in these experiments was to determine how resist contrast affects exposure dose latitude. Increased contrast is shown to improve the resolution of patterned features, but electrical linewidth data demonstrates a degradation of process latitude with respect to exposure dose. That is, linewidth variation due to either the proximity effect or focus variation will increase with increasing resist contrast. Lastly, a simple relationship is derived which enables one to predict immersion development time as a function of resist contrast.

A positive novolac-based resist, WX-214, developed by Olin Hunt Chemical, has been investigated for use with the commercial electron beam lithography systems, AEBLE 150 and MEBES® III. The WX-214 yielded a sensitivity of 16 pC/cm², a high resolution of 0.25μm lines and spaces, and an excellent dry etching resistance for pattern transfer. The results on the characterization of the resist and the development of a process for thin and thick films are presented.

A novel, aqueous alkaline developable, sensitive electron beam resist is described. This resist is a three component system consisting of a novolak resin, aminoplast, and a radiation sensitive acid generator (RSAG). The resist has demonstrated high resolution (0.3 μm grating in 0.5 μm thick resist) with under 5uC/cm² exposure dose. Furthermore, the resulting resist images exhibit dry etch stability comparable to optical positive novolak resists. This paper describes the chemistry of this novel resist system. The mechanism of the crosslinking reaction is discussed using data from GPC, FT IR and GCMS as analytical probes. The variation of sensitivity and contrast with resist composition has been analyzed as well. The paper addresses the nature of the post exposure "dark reaction" in this resist and compares it to other electron beam resists (eg. COP) known to exhibit a strong time dependence on processing. Electrical linewidth studies and scanning electron microscopy data are employed in these studies.

A two-layer resist process for the rapid direct-write e-beam microfabrication of nanometer-size structures is reported. The resist structure had a top layer of a sensitive positive organosilicon e-beam resist, poly(3-butenyltrimethylsilane sulfone) (PBTMSS), and a bottom layer having high chemical, thermal and mechanical stability, e.g., hard-baked Novolac, polyimide or diamond-like carbon (DLC). Periodic patterns with a pitch of >-60 nm have been obtained. Double-channel planar-buried-heterostructure distributed-feedback 1.3-μm lasers incorporating 2025-nm-pitch λ/4-shifted gratings fabricated using the reported process had excellent spectral and power characteristics.

A practical design of 0.1 cm diameter, 10 KW e-beam power, point x-ray source with v-shaped slotted rotating target is discussed. This point x-ray source can give penumbra--2 intra-wafer-distortion trade-off resolution of 0.13 pm and inverse-throughput for 25cm^-2 sensitivity resist of 1.8 s•cm-1. Temporal temperature rise for 7 cm slot radius and 50 s-1 revolution remain within 260 °C. Effect of radiation cooling by stacked fins are calculated. Thus estimate average temperature rise amounts to 490°C over cooling temperature. Estimated temperature rise of rotating axis is 300 °C. Effect of stacked fins as evacuation resistance is also discussed. We can maintain e-beam chamber within 10^-8 torr by using fero-fluidic seal working at 10-8 torr condition.

A novel process for fabricating x-ray masks of submicron gold patterns using a copper plating base is presented and discussed in detail. In the E-beam writing of x-ray masks, the trilevel resist layers and the metal layer for x-ray absorber patterning cause a proximity effect which determines the masks' resolution. Based on E-beam simulations and experimental results, copper plating base is selected as the best metal-layer material to reduce the above effect. To fabricate submicron gold patterns on the copper base, two gold-electroplating steps are newly introduced. These are strike plating and pulse-current plating. Stress change in the plated gold and positional accuracy changes are also measured throughout the heating process. Finally, sequential steps for the fabrication of x-ray masks with plating base are shown.

A three layer resist process for gate lift-oft on Gallium Arsenide MIMICs by electron Dean and optical lithographies are described. The electron beam lithography process consists of Poly (Dimethyl Glutarimide) PMGI as tne planarizing layer, a Plasma Enhanced Chemical Vapour Deposition silicon nitride (SiN) as an intermediate barrier layer and Poly (Methyl methacrylate), PMMA, as the top imaging layer. The PivimA is exposed by Cambridge Electron beam system EBMF 6.4 at 20kev and developed in Methyl Ethyl Ketone/Iso Propyl Alcohol. The pattern is then transferred to the SiN layer by cF4/o2 plasma etcning. The SiN layer is then used as the mask to transfer the pattern to the PMGI layer by 02 kteactive Ion Etching until tne GaAS is exposed. The various processing parameters are optimized to obtain lip or overnang suitable for lift-off with 0.20μm gate dimension. After the GaAS has been recessed (to reduce the parasitic source resistance), a thick 9000Å Ti/Pt/Au gate metal is evaporated and the unwanted gate metal is lifted oft using PMGI stripper. To use the three layer resist process in optical litnograpny, the MG.'. planarizing layer and PECVD SiN layer is used along with optical pnotoresist AZ1450J as a top imaging layer. inc sofcbake, uV exposure dose (436 nm) and development time for AZ145UJ are optimized to obtain 0.5μm to 1.0μm gate dimensions. The etch parameters for the pattern transfer to SiN and tnen to PMGI layers are same as in tne above process. The process levels such as mesa, source/drain, contact and metal levels for GaAs mlivilt,s are defined by UV lithography (Karl Suss contact aligner) using single layer pnotoresist. A nign overlay accuracy is obtained by use of gold metal Dumps as registration marks for aligning tne electron Dean exposed gate to optically exposed source/drain channel. Thus a higher tnrougnput and better linewidtn control are obtained using electron beam/optical lithography tecnniques. This approach is currently used to fabricate a 0.20μm gate Metal Semiconductor Field Effect Transistors on GaAS. These results are discussed in detail.

The growing interest in the use of Gallium Arsenide semiconductor materials has presented many opportunities for device operational speed improvements but has also presented many problems for the device maker. In particular a whole new range of processing techniques have been needed which are significantly different to those used routinely in Silicon processing. In addition, to obtain the best operational characteristics, device feature dimensions, linewidth tolerance and overlay accuracies are significantly more demanding than current silicon practices require. This "lithographic challenge" is at its most extreme where microwave active components like MESFET transistors are required. Present day routine devices require 0.5 to 0.25 micron gate lengths whilst leading edge devices need 0.1 micron or below complicated by the need for fabrication in three dimensions for "T" section structures. These are necessary to provide adequate gate conductivity and power handling whilst maintaining the narrow gate length contact.

This paper discusses the concept of pattern personality and its application to the characterization of different software and technological aspects in E-Beam direct write lithography. In this approach the personality of a pattern is related to a spectrum of the characteristic dimensions of a design. We explain simple techniques to obtain these spectra and indicate how they can be implied to predict and decide on the best writing strategy. Pattern personality is intended to be used as a compressed format that still contains enough information to base decisions on and compute the impact of processing steps on the pattern fidelity.

A high resolution trilayer resist system based on the copolymer e-beam resist P[MMA/MAA], an SiO2 interlayer, and a polyimide base layer will be described. High resolution reactive ion etch processes have been developed that minimize base layer undercut and provide for cleanly patterned windows for 150 nm thick aluminum lift-off. Residue formation on the base layer sidewalls after reactive ion etching has been found to depend on the substrate film composition. Linewidth variations as a function of exposure dose, development time, and reactive ion etch conditions will be discussed. The extent to which trilayer stencils can be used for high resolution reversal processes has been found to be limited by the polyimide thickness required for planarization and proximity effect reduction, aluminum film thickness required, and the minimum line space desired.

This paper describes a vapour coating technique for depositing polycyanoacrylate films up to 8um thick on semiconductor substrates. These films are suitable for use as EB/DUV resists and we present their measured characteristics. Vapour-deposited films have better plasma etching resistance than similar spun-on films.

An e-beam system is described which has been used to perform the final, customisation lithography on gate array chips supplied by several manufacturers. As not all of the types of gate array involved possess registration marks intended for e-beam use, an advanced registration technique employing cross-correlation has been developed to make use of such structures as are available. Electron-optical distortions have been simply corrected by using gate array chips themselves as calibration targets. The registration system is capable of acceptable performance at very low signal-to-noise ratios, and is therefore well suited to situations where the registration marks are deeply buried, e.g. in gate arrays with multiple metal levels.

Over the past several years, CMOS technology has been continuously driven to achieve enhanced performance and higher density. The resulting reduction in semiconductor dimensions has surpasssed the limits attainable by the most advanced optical lithography tools. As a result, the utilization of electron beam lithography direct writing techniques to satisfy VLSI patterning requirements has increased significantly. In principle, variable shaped electron beam systems are capable of writing linewidths down to at least 0.1 micron. However, the successful application of sub-micron scaling principles to device fabrication involves an integration of tool capability and resist process control. In order to achieve the realization of improved CMOS device performance and circuit density, sub-micron ground rules (line width control and overlay) must be satisfied over the full chip. This paper reports on a high performance, fully scaled 0.5 micron CMOS technology developed for VLSI appli-cations. Significant gains in both density and performance at reduced power supply levels are realized over previously reported 1.0 micron technology. The details of the integrated lithography strategy used to achieve these results are presented.

A nanometric electron beam lithography system was developed with 0.1 um resolution using 0.03 μm electron beam. To get practical writing speed of 1 wafer/ hr with 0.1 μm resolution, many new technologies were developed in the system. Here, the high speed data control circuit is precisely described. It consists of a pattern generator (a buffer memory, a framing processor, decomposition processor and correction processor ) and a beam deflection controller.

In this work, we studied reproducibility and yield in the fabrication of quarter-micron and sub-quarter-micron gates for GaAs FETs. To achieve reproducible gate length and high gate yield, an optimized lift-off process was used in conjunction with variation in the e-beam writing strategy. Statistical analysis of several wafers was made for each gate length at a given processing and exposure condition. It was observed that the gate length obtained was dependent on the exposing electron beam diameter, which in turn is a functi©n of filament (LaB6) age. Reproducibility of gate length is independent of accelerating voltage. Both reproducibility and yield are improved by use of smaller field size. At 1.6-mm field, two adjacent pass exposures provided better reproducibility for quarter-micron gates than did single-pass exposure. The associated yield was higher than 95%.

We describe the proximity patterning using 28 kV, soft vacuum exposing electrons of silver, copper and gold containing metal-polymer composite films. The cross-linking of the metal doped polyamic acid, resulting in reduced solubility of exposed regions, leads to successful patterning following conventional wet development. The patterned films were found to contain the metal content redistributed, preferentially enriching the surface during the imidization cure, as supported by a variety of surface analysis methods.

A hybrid lithography technique is described in which selected levels are fabricated by high resolution direct write electron beam lithography and all other levels are fabricated optically. This technique permits subhalf micron geometries and the site-by-site alignment for each field written by electron beam lithography while still maintaining the high throughput possible with optical lithography. The goal is to improve throughput and reduce overall cost of fabricating MIMIC GaAS chips without compromising device performance. The lithography equipment used for these experiments is the Cambridge Electron beam vector scan system EBMF 6.4 capable of achieving ultra high current densities with a beam of circular cross section and a gaussian intensity profile operated at 20 kev. The optical aligner is a Karl Suss Contact aligner. The flexibility of the Cambridge electron beam system is matched to the less flexible Karl Suss contact aligner. The lithography related factors, such as image placement, exposure and process related analyses, which influence overlay, pattern quality and performance, are discussed. A process chip containing 3.2768mm fields in an eleven by eleven array was used for alignment evaluation on a 3" semi-insulating GaAS wafer. Each test chip contained five optical verniers and four Prometrix registration marks per field along with metal bumps for alignment marks. The process parameters for these chips are identical to those of HEMT/epi-MESFET ohmic contact and gate layer processes. These layers were used to evaluate the overlay accuracy because of their critical alignment and dimensional control requirements. Two cases were examined: (1) Electron beam written gate layers aligned to optically imaged ohmic contact layers and (2) Electron beam written gate layers aligned to electron beam written ohmic contact layers. The effect of substrate charging by the electron beam is also investigated. The resulting peak overlay error accuracies are: (1) Electron beam to optical with t 0.2μm (2 sigma) and (2) Electron beam to electron beam with f 0.lμm (2 sigma). These results suggest that the electron beam/optical hybrid lithography techniques could be used for MIMIC volume production as alignment tolerances required by GaAS chips are met in both cases. These results are discussed in detail.

Gaussian e-beam pattern generators should use the highest obtainable brightness of the electron source to improve the throughput for a given definition 1. Therefore in these machines it is desirable to use sharp-tip cathodes. When LaB6 is the cathode material the optimization of the relevant parameters is very difficult due to the non-homogeneous emission pattern 2 . Usually direct observation of the source is not possible in these production machines. The only means which give an insight into the electron-optic column are emission current, beam current, spot characteristics and settings of alignment coils and lenses. Moreover, when only one alignment unit is used with several lenses, several local optima can exist in the alignment. As a result, the optimum of these non-orthogonal parameters is difficult to obtain, even for a skilled operator. Mang pattern generators avoid these difficulties by using a flat-tipped cathode, but at the penalty of lower brightness. Therefore, software has been developed to achieve the optimum setting automatically using the knowledge of the dynamic behaviour of the different parameters to limit the multi-dimensional space in which these parameters have to be optimised. This limitation is necessary because a search through all possible settings would require an unacceptable amount of machine time. For a full understanding of the algorithms an explanation of the physical processes is necessary. Also the effect of handling by the operator and the change of parameters with time must be included. The software adjusts the cathode temperature, according to the specified brightness (while never overheating the tip), selects the correct part of the beam and sets the required spotsize. The optimization time is dominated b physics and electronics and not b the algorithms. The adjustment time of the tip temperature is determined mainly b the heat capacitance of the complete cathode assembly mounting; the time to find the correct lobe and alignment is determined by the time constant of the alignment coils and drivers and the spotsize setting by the time constants of lenses and drivers. A short overview will be given about the conditions for use of LaB6 as a cathode material to obtain high brightness and long life, particularly the vacuum specifications (P< 2.10E-8 torr) and filament temperature (T< 1800 K).

Direct write electron beam (EB) lithography is expected to write a very fine wafer pattern below half micron for the development of the comming generation ULSIs. But direct write EB lithography has two main peculiar problems for obtaining such a very fine resist pattern on an uneven topography of a processed wafer. One is a pattern dimension deviation from the designed value due to resist topography and proximity effects. The other problem is pattern registration deviation due to charge-up in the EB-resist. In order to investigate the proximity effect. we evaluated the deposited energy density profile by a double gaussian Exposure Intensity Distribution ( EID ) function. The theoretical and experimental results showed that in a 2.2 micron thick trilayer planerizing resist system. both 0.5 micron isolated line and isolated space were simultaneously resolved in half micron thick top layer resist. To compensate the charge-up problem, we treated the bottom-layer by a brand-new ion shower material modification process. A 40 KV proton shower irradiation decreased the resistance of the bottom layer. The charge of the electron beam was dissipated through the bottom layer resist. The resultant half micron rule 16 M-bit DRAM patterns were compared with the optically exposed tri-level resist patterns. The optically exposed patterns also had an optical proximity effect and half micron patterns were not resolved even adopting the contrast enhancement lithographic ( CEL ) technology. On the other hand, we successfully obtained 16M-bit DRAM patterns on the uneven topography of the processed wafer using EB direct write.

Electron Beam Lithography has emerged as the predominant tool for high accuracy mask making. Two basic types of systems have been developed over the past twenty years for mask making operations: Raster scan-spot beam systems conceived by Bell Laboratories and commercialized by Perkin-Elmer as the MEBES Series and Vector Scan-Shaped beam systems such as the internally ysed EL Series by IBM or the commercially available JBX-6A Series developed by JEOL. The remainder of this paper will describe the current model of the JEOL Series, the JBX-6AIII that has evolved over the past 10 years to provide a high throughput, high accuracy mask making system. This system has been improved over previous models in the series with the addition of a high speed data transfer unit and real time shot partitioning function in order to match pattern generation to pattern writing speeds. At the same time the writing accuracies and shot placement size and accuracies have been improved to permit VLSI 1X reticles to be fabricated.

The AlGaAs/GaAs selectively doped heterostructure transistor (SDHT) demonstrates reduced short channel effects in comparison with conventional GaAs MESFETs since the channel of the FET is confined to a two dimensional electron gas. Very short propagation delays have been demonstrated previously for submicron direct coupled FET logic circuits'. In order to reliably produce submicron gate devices, a lift-off method for defining 0.50 pm gates in AlGaAs/GaAs SDHT circuits has been developed. The gate is defined in a tri-level resist system consisting of EBR-9 as the imaging electron beam resist, germanium as the intermediate level, and PMGI as the bottom resist. The EBR-9 was chosen for its sensi-tivity and high feature resolution. Germanium insures good adhesion to both resists, and is an excellent etch mask for the PMGI. The PMGI was selected because the resist can be chemically removed at low temperatures, making it suitable for a lift-off process. Electron beam direct writing, utilizing an EBES 1112 writing system, defines the gate pattern in the EBR-9 imaging layer of the trilevel resist. EBES III is a 20 keV, 20 MHz raster scan machine with a 0.25 μm morainal spot size. Machine throughout is approximately two 50 mm wafers/hour. A global alignment scheme references the gates to the gold metal based ohmic level pattern. Following the wet development of the imaging resist, the germanium is reactive ion etched using SF6 as the etchant gas. The PMGI is subsequently etched in an oxygen plasma. In order to facilitate the lift-off process the etch is tailored to reproducibly provide a small amount of controlled undercut in the resist. The new process is compatible with the metallization and self aligned recess etch of the SDHT technology. The methods for developing the resist, maintaining gate length, and controlling the undercut in the trilevel will be discussed. In addition, the performance of devices and circuits fabricated using this process will be discussed.