This PDF file contains the front matter associated with SPIE Proceedings Volume 10775, including the Title Page, Copyright information, Table of Contents, Author and Conference Committee lists.

The multi-trigger resist (MTR) is a new negative tone molecular resist platform for electron beam lithography, as well as extreme ultraviolet and optical lithography. The performance of xMT resist, the precursor to MTR resist, which shows a good combination of sensitivity, low line edge roughness and high-resolution patterning has previously been reported.[1] In order to overcome limitations induced by acid diffusion, a new mechanism - the multi-trigger concept - has been introduced. The results obtained so far as the behaviour of the resist is driven towards the multi-trigger regime by manipulating the resist formulation are presented. A feature size of 13 nm in semi-dense (1:1.5 line/space) patterns, and 22nm diameter pillar patterns are demonstrated in electron beam, and 16 nm half-pitch resolution patterns are demonstrated in (extreme ultraviolet) EUV. An improvement in the LER value is seen in the higher MTR formulations.

A numerical study of EUV Bragg mirrors with superstructures is presented. These modifications of the standard Mo/Si mirror are periodic superlattices as well as depth grading of the superlattice multilayers. The main results concern a narrowing of the normal incidence peak and all-angle reflection at 13.5 nm. Best results are obtained with a combination of superlattices with 4 and 5 superperiods and depth grading. The effect of the spectral width of the EUV source is also taken into account.

Operating maskless, massively parallel electron beam direct write (MEBDW) is an attractive alternative to optical lithography in micro and nano device manufacturing. Mapper Lithography develops MEBDW tools able to pattern wafers, for application nodes down to 28nm, with a throughput around one wafer per hour. A prototype tool from this series, named FLX-1200, is installed in the CEA-Leti clean room. This paper reviews the current performances of this prototype and the methodology used to measure them. On standardized exposure, consisting of 100 fields of 5×5mm² exposed, in less than one hour, on 300mm silicon wafers, we obtained CD uniformity below 10nm (3σ) and LWR of 4.5nm for 60nm half pitch dense lines. We also demonstrate capability of 15nm and 25nm (3σ) for stitching and overlay errors respectively.

Multiple electron beam direct write lithography is an emerging technology promising to address new markets, such as truly unique chips for security applications. The tool under consideration, the Mapper FLX-1200, exposes long 2.2 μm-wide zones called stripes by groups of 49 beams. The critical dimensions inside and the registration errors between the stripes, called stitching, are controlled by internal tool metrology. Additionally, there is great need for on-wafer metrology of critical dimension and stitching to monitor Mapper tool performance and validate the internal metrology. Optical Critical Dimension (OCD) metrology is a workhorse technique for various semiconductor manufacturing tools, such as deposition, etching, chemical-mechanical polishing and lithography machines. Previous works have shown the feasibility to measure the critical dimension of non-uniform targets by introducing an effective CD and shown that the non-uniformity can be quantified by a machine learning approach. This paper seeks to extend the previous work and presents a preliminary feasibility study to monitor stitching errors by measuring on a scatterometry tool with multiple optical channels. A wafer with OCD targets that mimic the various lithographic errors typical to the Mapper technology was created by variable shaped beam (VSB) e-beam lithography. The lithography process has been carefully tuned to minimize optically active systematic errors such as critical dimension gradients. The OCD targets contain horizontal and vertical gratings with a pitch of 100 nm and a nominal CD of 50 nm, and contain various stitching error types such as displacement in X, Y and diagonal gratings. Sensitivity to all stitching types has been shown. The DX targets showed non-linearity with respect to error size and typically were a factor of 3 less sensitive than the promising performance of DY targets. A similar performance difference has seen in nominally identical diagonal gratings exposed with vertical and horizontal lines, suggesting that OCD metrology for DX cannot be fully characterized due to lithography errors in gratings with vertical lines.

In this paper the bias table models for the wafer scale SmartNIL™ technology are addressed and validated using complete Scanning Electron Microscopy (SEM) characterizations and polynomial interpolation functions. Like the other nanoimprint lithography (NIL) technics, this replication technology is known to induce Critical Dimension (CD) variations between the master and the imprint, due to polymer shrinkage, soft stamp deformation or thermal expansion. The bias between the former and final object follows peculiar rules which are specific to this process. To emphasis these singularities, Critical Dimension (CD) uniformity analyses were analyzed onto 200 mm wafers imprinted with the HERCULES® NIL equipment platform. Dedicated masters were manufactured to capture the process signatures: horizontal and vertical line arrays, local densities ranging from 0.1 to 0.9 and minimum CD of 250 nm. The silicon masters were manufactured with 248 optical lithography and dry etching and treated with an anti-sticking layer from Arkema. CD measurements were made for the master and the replicates on 48 well selected features to build interpolations. The bias table, modelled by polynomial functions with a degree of 5 for the density and a degree of 3 for the CD, are compared between horizontal and vertical features, and between the center and the edge of the wafers. Finally the focus is made on the validation of the interpolations by comparing the computed bias and the experimental data.

Lithography requirements for Advanced Packaging & MEMS are very different compared to mainstream semiconductor industries’ needs. Even if the market entry barrier is much lower in the “More than Moore” market, customer adoptions needs are higher in the packaging area with respect to resolution, overlay, sidewall angle, and depth of focus (DOF), wafer handling for wafer bow and backside alignment. Key technical trends, requirements and challenges regarding the lithography technologies will be addressed in this paper. In addition, more insights on the current and emerging lithography methods for More than Moore devices will be included, as well as market forecast, competitive landscape of the major equipment suppliers addressing these fields.

Photolithography masks require a periodical inspection and cleaning. The visual inspection is often paired with a mask air blowing to remove eye visible particles. If these steps are run manually they are really critical for mask integrity in terms of contaminations, scratches, fingerprints, pellicle damage... All these potential issues arise during the mask certification process causing mask repelliculization, and, in the worst case, mask scrap with drawbacks linked to production aspects: quality (repetitive defects), cost (mask repels/remake), production lots on hold, non-linear production WIP and non-respect of production commitments. AG8-AGM photolithography engineering team in collaboration with “Gusmini attrezzature industriali” developed a tool called “CK-MASK” able to handle 6” masks and to reduce the risks connected to masks inspection and blowing.

A fundamental aspect for the economic success of a semiconductor production is a low level of costs per wafer. A substantial part of these costs per wafer is accounted by personnel costs. For this reason, it is desirable to reach the lowest possible level of personnel costs. Mainly this is achieved by increasing the degree of the factory automation. To increase the degree of factory automation, various approaches are conceivable and in use. We were at the time the first 12”-fab worldwide and we were equipped with an OHT (Overhead Hoist Transfer) system of the first generation to transport to and load wafer pods on process equipment and wafer stockers. That means, that the complete wafer handling took place automatically. Viewed with a certain distance, the fab as a whole showed a high level of automation. However, in the lithography it was necessary to handle reticles manually. Figure 1 shows the distribution between the automated wafer handling and the manual done parts reticle handling and necessary tool assist. The efforts for manual reticle handling and the resulting personnel costs contradicted the requirements of a highly automated manufacturing. An investigation about possible reticle automation scenarios by using AGV (Automated Guided Vehicles) or OHT to improve the lithography automation level resulted in non-acceptable investments in relation to the saved personnel costs. As a result, further activities to automate reticle handling have been avoided. But driven by the end of live situation of the used OHT system, a retrofit of the system in 2017 offered the possibility to install additionally to the lot OHT system a reticle OHT option. In conjunction with the findings of the above investigation, this new situation led to the decision to install this option to save the personnel costs of manual reticle handling. Introductory in this paper, we would like to compare briefly conceivable automation scenarios by using AGV and OHT systems. We describe the advantages and disadvantages of both systems arising from our present situation. We justify why only the use of an OHT makes sense for us. The main part of the paper is dedicated to the way from the ended OHT hardware startup to the running automated reticle handling. First of all, we introduce the machinery used. The majority of the exposure equipment was not intended for OHT loading by tool manufacturer. We explain the modifications needed to allow a reticle loading of the exposure tools by OHT. One key factor in getting the system up and running is the control of the exposure tools by host commands. These sequences are used to enable the tool operation without operator-tool interaction. Based on the reticle load and unload strategy, we explain basics of our used exposure tool control. Another key factor is the system control algorithm. The whole reticle operation is controlled by a rule based dispatching system. The rules used combine robustness and necessary performance emphasizing the robustness of the system. The limitations of this rule based dispatching system are discussed and the use of a mathematical solver system recommended. An important aspect of the introduction of the system is the fact that the exposure systems, the OHT and the reticle stockers were used to create a network of machines. This machine network requires functional monitoring approaches that are new to us. We consider possibilities to display status information of this complex network as simply as possible. The aim is to enable fast and efficient troubleshooting within the network. Furthermore, this newly created machine network entails some intrinsic risks. The main risk of complete failure due to the failure of a sub component and ways to minimize this risk are discussed. A summary of the practical experiences during the construction phase of several months completes the main part of this work. It is expected that in continuous operation the demands on the performance and the robustness of the system will increase. In conclusion, we would like to point out possibilities for future system optimization. Based on the current state of knowledge and the implementation costs we will try to evaluate these. Finally, we would like to comment on the title's restriction "almost". We explain why a completely automated lithography, which means including the additional automation of tool assists, is not possible from our current perspective.

Mask data are presented which demonstrate local registration errors that can be correlated to the writing swathes of stateof-the-art e-beam writers and multi-pass strategies, potentially leading to systematic device registration errors versus design of close to 2nm. Furthermore, error signatures for local charging and process effects are indicated by local registration measurements resulting in systematic error, also on the order of 2nm.

Accurate calibration of the optical and resist parameters is invaluable for the computation of the dose distribution needed to fabricate a desired non-binary photoresist topography. This paper presents a method for precisely evaluating the 3D point spread function (PSF) and model parameters for the resist processes in laser grayscale lithography. The 3D PSF and resist model parameters were determined by fitting a detailed model of the grayscale process to experimental measurements of an array of test patterns. Measuring the entire 3D profile provides more data for process calibration, and therefore a more accurate model. The derived model parameters were applied to correctly predict the topography of sawtooth patterns.

Designs for photonic devices on silicon relies on non-Manhattan features such as curves and a wide variety of angles. Reticle Enhancement Techniques (RET) that are commonly used for CMOS manufacturing now are applied to curvilinear data patterns for the same reasons of enhancing pattern fidelity. Common techniques for curvilinear data processing include Manhattanization, jog removal, and jog alignment. We propose a novel method of describing curvilinear shapes in terms of curves reconstructed between control points. Such representation of curvilinear shapes brings many benefits in terms of pattern description (improved fidelity, file compaction), correction and verification. For example, it allows smooth displacements during the design correction procedure for process effects. The conventional correction by biasing each fragment illustrates the curve-based biasing where only the control points have been moved and the corrected shape was then reconstructed by connecting the control points in their new positions by the new curves. This method results in faster computation because there are fewer locations to adjust geometry, easier convergence and intrinsic continuity between edges. It also affords significant reduction of the design file size. Besides processing curvilinear pattern data, verification is also required after any original pattern modifications. Mask Rule Checks (MRC) are considered as standard step in any design data preparation flows, but the conventional MRC algorithms are conceived for Manhattan designs and as such they often result in numerous false errors or even missing errors when applied to photonics or ILT (Inverse Lithography Technology) designs. In addition, MRC for photonic layouts require much more than basic width and space checking. We developed a verification technology compliant with curvilinear layouts. The new MRC technique is also based on curve representation of the original design comparing directly the curves instead of the straight fragments. It permits to have only one error flag per curve instead of multiple errors seen in fragment-by-fragment MRC.

The technical roadmap adopted by the semiconductor industry drives mask shops to embrace advanced solutions to overcome challenges inherent to smaller technology nodes while increasing reliability and turnaround time (TAT). It is observed that the TAT is increasing at a rapid rate for each new ground rule. At the same time, productivity and quality must be ensured to deliver the perfect mask to the customer. These challenges require optimization of overall manufacturing flows and individual steps, which can be addressed and improved via smart automation. Ideally, remote monitoring, controlling and adjusting key aspects of the production would improve labor efficiency and enhance productivity. It would require collecting and analyzing all available process data to facilitate or even automate decision-making steps. In mask shops, numerous areas of the back end of line (BEOL) workflow have room for improvement in regards to defect disposition, reducing human errors, standardizing recipe generation, data analysis and accessibility to useful and centralized information to support certain approaches such as repair. Adapting these aspects allows mask manufacturers to control and even predict the TAT that would lead to an optimized process of record.

For advanced technology nodes, the patterning of integrated circuits requires not only a very good control of critical dimensions but also a very accurate control of the alignment between layers. These two factors combine to define the metric of inter-layer edge placement error (EPE) that quantifies the quality of the pattern placement critical for yield. In this work, we consider the inter-layer EPE between a contact layer with respect to a poly layer measured with SEM contours. Inter-layer EPE was measured across wafer for various critical features to assess the importance of dimensional and overlay variability. Area of overlap between contact and poly as well as contact centroid distribution were considered to further characterize the interaction between poly and contact patterns.

SEM metrology is widely used in microelectronics to control patterns dimensions after many processes, especially patterning. Process control is achieved by verifying that experimental dimensions match targeted ones. However SEM metrology may give erroneous measurements if strong charging occurs. Charging effect impacts on the SEM image contrast and introduces artefacts. This article intends to report on the modeling of the physical phenomena occurring when the electron gun scans a sample and how charging effect occurs. For this, charge dynamics are modeled by taking into account the drift kinetics and the diffusion of electrons. The corresponding Partial Differential Equation system is solved using FEniCS open software. First, we show that when only top view measurement are modeled, the typical contrast of SEM pictures can not be predicted. Second, cross section views are modeled. This time, the expected contrast behavior is obtained. Finally, a full 3D simulation is presented.

We use deep supervised learning for the Poisson denoising of low-dose scanning electron microscope (SEM) images as a step in the estimation of line edge roughness (LER) and line width roughness (LWR). Our denoising algorithm applies a deep convolutional neural network called SEMNet with 17 convolutional, 16 batch-normalization and 16 dropout layers to noisy images. We trained and tested SEMNet with a dataset of 100800 simulated SEM rough line images constructed by means of the Thorsos method and the ARTIMAGEN library developed by the National Institute of Standards and Technology. SEMNet achieved considerable improvements in peak signal-to-noise ratio (PSNR) as well as the best LER/LWR estimation accuracy compared with standard image denoisers.

The usage of convolutional neural networks (CNN) on images is spreading into various topics in lot of industries. Today in the semiconductor industry CNN are used to perform Automatic Defect Classification (ADC) on SEM review images in almost real time and with level of success as high as trained operators can do or more [1,2]. The possibilities to get new kind of information from images offer to engineers multiple potential usages. In this paper we propose to present derivatives usages of CNN applied to the CD-SEM metrology with specific focus on an application to detect undermelted microlens in our imager process flow [3]. CD-SEM metrology is used to perform Critical Dimension (CD) measurement on almost all patterning steps in the wafer cycle (after lithography and after etch). CNN allows us to get more information from pictures than only dimensions measured by the CD-SEM used to feed a control card. In our imager process flow we have steps to form microlenses. The microlens process fabrication consists in a first lithography step where microlens matrix is defined in resist. The result is a matrix of quite square parallelepipoid microlenses followed by a melting step in order to reflow resists and eventually form microlens with spherical cap shape. The figure 1 shows the evolution of microlens shape in function of melting process time.

Mitigation of mask 3D effects is essential for EUV imaging of high resolution features. The 3D EUV masks give rise to phase effects over the diffracted orders and potentially distort the image on the wafer. These phase effects may reduce contrast, result in pattern shifts and result in best focus variations on wafer. Two variations on the current absorber are investigated to their impact on reduction of M3D effects and impact on image quality. Use of high-k absorber materials allows for thinner masks to be used and helps to reduce averse M3D effects. Attenuated phase shift masks work by allowing a higher optical transmission while giving a phase shift to the transmitted light, which further improves image contrast on wafer and also enables thinner absorbers to be used. Attenuated PSM absorbers show a stronger variation in imaging performance through incidence angle onto the reticle. It has been shown that this results in a variation in imaging performance for varying features and pitches. Specifically of interest is how NILS through focus is influenced by the different absorbers. Phase shift masks show better performance for NILS through focus on contact holes, and high-k masks work well for dense lines.

Grayscale lithography is a well-known technique for three dimensional structuring of a photo sensitive material. The 3D structuring of the photoresist is performed by a spatially variable exposure. Pixelated grayscale mask structures are defined to achieve the desired 3D resist patterns by locally variable transmittance values. Within power semiconductor processing, grayscale techniques could beneficially be applied in different process steps. Several ideas come to mind for process simplification, alternative integration scheme and more, e.g. the realization of 3D resist patterns for implant applications in order to control the doping depth and profiles and their influence on device parameters. In order to make the grayscale process useful for manufacturing of semiconductor devices it is necessary to master and consider the inherent process variability. Lithographic simulation is used to optimize the sub-resolution photo-mask features and to predict the final resist shape and its variability. Device simulation for a DMOS device, used in our 130nm technology node, shows that the device performance would benefit from an attenuation of the implant dose in the center of the device, which could be achieved by creating a resist island with reduced resist thickness in the center of the drawn implant opening of the DMOS device. In order to achieve the desired target geometry of the implant resist mask, simulations with Sentaurus Lithography have been performed resulting in a suitable mask design and lithographic process. We will demonstrate the development of the grayscale litho-process based on the needs of an implant scheme that is going to be used for a DMOS device, with respect to process stability and achieved resist mask dimensions.

Overlay is a one of the most critical design specifications in semiconductor device manufacturing. Any state-of- the-art production facility has overlay metrology in place to monitor overlay performance during manufacturing and to use the measurements for overlay control. Especially since the introduction of multi-patterning, with its tight overlay requirements and increased number of process steps, there has been an increased need for additional metrology. Overlay metrology brings cost-added value to semiconductor device manufacturing and it should be reduced to a minimum to keep costs at acceptable levels, which can be a challenge in the multi-patterning era. Replacing some real overlay measurements with predicted values, referred to as virtual overlay metrology, could be a viable solution to address this challenge. In this work, we develop virtual overlay metrology and aim at predicting the overlay for a series of implant layers. To this end, we apply machine learning algorithms, and neural networks in particular, to build a complex non-linear model directly from data. Our model takes a set of features that are designed based on the physical concepts of overlay and outputs the overlay map of a target layer. The features include overlay of another implant layer of the same wafer, exposure tool fingerprints, scanner logging, and process data. We evaluate our model using production data and we show the prediction performance for the raw overlay, as well as for the correctable and non-correctable overlay errors.

A novel technique to realize large quantities of stacked multifunctional anisotropic nanoparticles with narrow size distribution is presented. Through the combination of Ultraviolet Nano-Imprint Lithography (UV-NIL), physical vapor deposition and subsequent lift-off processes we fabricate and disperse these particles in solution for the use in biomolecular sensing applications. Compared to chemical nanoparticle synthesis our approach holds several advantages. First, one can control the nanoparticle shape by choosing an appropriate nanopattern for the UV-NIL process. Second, we can choose the composition of the nanoparticles as the materials are deposited layer-wise by sputter deposition. Third, we can fabricate nanoparticles with very small geometrical variations. This is in contrast to chemical synthesis methods where the layer thicknesses and particle size distribution are harder to control.

With the substantial surge in the need for high-end masks it becomes increasingly important to raise the capacity of the corresponding production lines. To this end the efficient qualification of matching tools and processes within a production line is of utmost relevance. Matching is typically judged by the processing of dedicated lots on the new tool and process. The amount of qualification lots should on the one hand be very small, as the production of qualification plates is expensive and uses capacity of the production corridor. On the other hand the strict requirements of high-end products induce very tight specification limits on the matching criteria. It is thus often very difficult to assess tool or process matching on the basis of a small amount of lots. In this paper we expound on a machine learning based strategy which assesses the mask characteristics of a qualification plate by learning the typical behavior of these characteristics within the production line variations. We show that by careful selection of reference production plates as well as by setting specification limits based on the production behavior we can manage the qualification tasks efficiently by using a small number of masks. The specification characteristics as well as the specific limits are selected and determined using a Naïve Bayes learner. The resulting performance for prediction of tool and process matching is assessed by considering the resulting receiving operator curve. As a result we obtain an approach towards the assessment of qualification data which enables engineers to assess the tool and process matching using a small amount of matching data under the constraint of substantial measurement uncertainties. As an outlook we discuss how this approach can be used to examine the reverse question of detecting process failures, i.e. the automated ability to raise a flag when the current production characteristics start to deviate from their typical characteristics. Overall, in this paper we show how the rapidly evolving field of machine learning increasingly impacts the semiconductor production process.

The durability of deposition repairs of two different e-beam mask repair tools has been examined and compared in this work. To obtain this data, clear defects on production masks have been repaired with both tools. In between these repairs the mask was used for production and gathered exposure dose accordingly. The increase of transmission and hence the degradation of the deposition has been determined by AIMSTM. We could confirm that one tool/process shows better stability of the depositions than the other.

With CMOS technology nodes going further into the realm of sub-wavelength lithography, the need for compute power also increases to meet runtime requirements for reticle enhancement techniques and results validation. Expanding the mask data preparation (MDP) cluster size is an obvious solution to increase compute power, but this can lead to unforeseen events such as network bottlenecks, which must be taken into account. Advanced scalable solutions provided by optical proximity correction (OPC)/mask process correction (MPC) software are obviously critical, but other optimizations such as dynamic CPU allocations (DCA) based on real CPU needs, high-level jobs management, real-time resource monitoring, and bottleneck detection are also important factors for improving cluster utilization in order to meet runtime requirements and handle post-tapeout (PTO) workloads efficiently. In this paper, we will discuss tackling such efforts through various levels of the “cluster utilization stack” from low CPU levels to business levels to head towards maximizing cluster utilization and maintaining lean computing.

We present both modeling and experimental results devoted to design, fabrication and characterization of metal covered hexagonal diffraction gratings. Variation of exposition and development time allow to modify the shape of the elementary cell, leaving the depth and periodicity unchanged. The fabrication process was modeled using real parameters of the lithography bench and the photoresist, substantially improving experimental results. The high quality of metal covered gratings is confirmed by excitation of plasmonic resonances, which are in a good agreement with theoretical predictions. The described approach allows to better understand plasmonic effects in 2D periodic structures and leads to an optimized design of plasmonic sensors.

Although conventional computer technology made a huge leap forward in the past decade, a vast number of computational problems remain inaccessible due to their inherently complex nature. One solution to deal with this computational complexity is to highly parallelize computations and to explore new technologies beyond semiconductor computers. Here, we report on initial results leading to a device employing a biological computation approach called network-based biocomputation (NBC). So far, the manufacturing process relies on conventional Electron Beam Lithography (EBL). However we show first promising results expanding EBL patterning to the third dimension by employing Two-Photon Polymerization (2PP). The nanofabricated structures rely on a combination of physical and chemical guiding of the microtubules through channels. Microtubules travelling through the network make their way through a number of different junctions. Here it is imperative that they do not take wrong turns. In order to decrease the usage of erroneous paths in the network a transition from planar 2-dimensional (mesh structure) networks to a design in which the crossing points of the mesh extend into the 3rd dimension is made. EBL is used to fabricate the 2D network structure whereas for the 3D-junctions 2PP is used. The good adaptation of the individual technologies allows for the possibility of a future combination of the two complementary approaches.

Although the critical dimension (CD) is getting smaller following the ITRS roadmap, the scanning electron microscope (CD-SEM) is still the most general purpose tool used for non-destructive metrology in the semiconductor industry. However, we are now dealing with patterns whose dimensions are of the same order of magnitude as the electron interaction volume and therefore, the usual edge-based metrology methods fail. Like scatterometry has extended the resolution of optical imaging metrology through complex modeling of light-matter interaction, some electrons-matter simulation models have been proposed. They could be used to improve accuracy and precision of CD-SEM metrology. However, these model-based approaches also face to fundamental limits mainly due to probe size with respect to the considered structure and noise. This paper analyses these limits assuming the model is perfect and the microscope has no systematic defect. In this simulation study, we have used the model proposed by D. Nyyssonen, assuming to perfectly represent the SEM effects in the image. The feature of interest is limited to isolated trapezoidal lines with various CD, sidewall angles (SWA) and heights. We have carried out the study with several beam energies, tilts and probe sizes. Surprisingly enough, sensitivity analysis shows that with typical noise amplitude, sidewall angle can be determined with a reasonable precision using SEM images. Single tilted beam SEM images can also bring advantage to measure patterns height. Since these precision figures depend on the geometries, we provide useful graphs giving the ultimate precision for various dimensions (CD, height, SWA).

Currently, Line Edge Roughness (LER) and Line Width Roughness (LWR) control presents a huge challenge for the lithography step in microelectronic industries. For advanced nodes, this morphological aspect reaches the same order of magnitude than the Critical Dimension, which leads to an increased power consumption by transistors and devices. Hence, the control of roughness needs an adapted metrology. This study proposes to manufacture roughness standard samples and their validation. These samples can be used as standards to evaluate the capabilities of several tools. The preliminary part of this study has been carried out with periodical roughness sample to demonstrate the metrology approach. Further, programming of roughness based on Power Spectral Density (PSD) with Auto-Correlation Function (ACF) model is used to achieve roughness close to the real roughness case. A description of how design programmed roughness has been made and its exposition in the real conditions are detailed in this study. Moreover, a specific methodology of control has been developed, the results obtained have been compared with design inputs and mostly validated by experimental processes. This work represents the first step of manufacturing roughness standard samples based on PSD model design.

Lithographical hotspot (LH) detection using deep learning (DL) has received much attention in the recent years. It happens mainly due to the facts the DL approach leads to a better accuracy over the traditional, state-of-the-art programming approaches. The purpose of this study is to compare existing data augmentation (DA) techniques for the integrated circuit (IC) mask data using DL methods. DA is a method which refers to the process of creating new samples similar to the training set, thereby helping to reduce the gap between classes as well as improving the performance of the DL system. Experimental results suggest that the DA methods increase overall DL models performance for the hotspot detection tasks.