Free-space digital optics may offer high speed system designers many benefits in the future. This paper explores these benefits within the switching domain, and it also identifies potential obstacles that must be circumvented if the technology is to find useful applications.

We have proposed a new three-dimensional optically coupled common memory (3D-OCC memory) to solve the problem of bus bottle neck in the multi-processor system with the shared memories. Three-dimensional-OCC memory consists of several memory layers vertically stacked and a block of data is simultaneously transferred among these memories using vertically optical interconnection. Three-dimensional-OCC memory acts as the real shared memory. Three-dimensional-OCC memory test chip has been fabricated using 2 micrometers CMOS technology. LEDs are integrated on the silicon test chip by using a newly developed micro-bonding technology. We observed the uniform photon emission from these LEDs. In addition, the basic operation of 3D-OCC memory for optical writing/electrical reading was confirmed using this test chip.

A 3:8 multiplex (MUX) data router operating at 100 MHz has been successfully demonstrated in the laboratory. A primary goal of this program was to show how `smart' optical interconnect technology could be implemented using address decoding as a detector. As a predecessor to crossbar technology, an optical MUX architecture based on global (4- dimensional), `smart' GaAs optoelectronic interconnect technology has been developed using high performance optoelectronic computing (HPOC) modules configured in an asynchronous transfer mode (ATM) protocol.

An integrated 3-D guided-free-space 4-stage optoelectronic fan-out (6 X 6, 2 X 6, 6 X 6 and 2 X 6) interconnect using WDDM is proposed and demonstrated together with 2 X 4 X 5 3-D optoelectronic fan-out using SDDM. This channel separation is one order of magnitude smaller than that using wavelength-selective detecting technique in WDDM. Signal to noise ratio of 57 dB is experimentally determined, with two channel 40 (2 X 4 X 5) fan-outs having a channel separation of 600 micrometers in SDDM. The interconnection scheme presented herein allows each pixel within a transmitting plane to communicate simultaneously and reconfigurably with many pixels in the subsequent planes in a truly three-dimensional feature. This system can utilize vertical cavity surface emitting laser diodes, photo detecting planes and planarized guided-free-space fan-out interconnects, allowing compact multi-stage integration. By using two-dimensional spatially separated or multiplexed hologram arrays on a thin light guiding plate, the interconnection capability is greatly enhanced as compared to other techniques. This novel optoelectronic interconnect should find widespread applications in microelectronics systems and fiber-optic communication networks. In this paper, we report the demonstration of a new solution that employs guided-free-space optical parallel fan-out interconnects. It takes advantage of such exclusive characteristics of optical interconnects as high packing density, massive single- wavelength fan-out and wavelength multiplexibility. Unlike the previously reported research, the interconnection scheme presented herein allows each pixel in a transmitting plane to communicate simultaneously and reconfigurably with many pixels in the subsequent planes with a truly three-dimensional (3-D) feature. Moreover, WD(D)M configuration can be maintained while extending into space-division-demultiplexing (SDDM) based on the fact that each VCSEL is spatially separated in the transmitting plane. As a result, each channel does not need to have many laser diodes operating at different wavelengths in order to facilitate the spontaneous communications with many pixels in the detecting planes. This new approach significantly reduces the fabrication requirements imposed on the laser diodes (with multiple output wavelengths) and on the photodetectors (with wavelength-selectivity). A one-to-one 2-D interconnect scheme is extended into a one-to-many 3-D one.

Custom designed surface-relief gratings are used to generate two-dimensional, uniform intensity beam arrays in several current digital free-space photonic system demonstrators. Although the design process for creating these gratings depends intrinsically on the size of the beam array; the optimization algorithm and the available computational resources ultimately determine the greatest complexity grating that is easily obtained. A new design algorithm is presented that has proven its ability to quickly design large beam array generators (128 X 128 and larger solutions) composed of either uniform intensity or arbitrary intensity beams. The algorithm produces two-dimensional non-separable binary phase or multiphase level solutions that yield a higher diffraction efficiency than separable dimension designs. Although the algorithm must optimize up to the order of 10⁶ parameters that determine the intensities of from 16 to 32 K beam intensities, a personal computer will generate solutions in a matter of a few minutes to a few hours. We evaluate the algorithm performance for a number of designs and demonstrate several patterns that have been fabricated onto fused silica substrates via microlithography and reactive ion etching.

We have designed, fabricated, and tested a prototype parallel ten-channel unidirectional optical data link. When scaled to production, we project that this technology will satisfy the following market penetration requirements: (1) up to 70 meters transmission distance, (2) at least 1 gigabyte/second data rate, and (3) $0.35 to $0.50 MByte/second volume selling price. These goals can be achieved by means of the assembly innovations described in this paper: a novel alignment method that is integrated with low-cost, few chip module packaging techniques, yielding high coupling and reducing the component count. Furthermore, high coupling efficiency increases projected reliability reducing the driver's power requirements.

The existing computer-aided-design tools in optoelectronics are reviewed and compared. The beam propagation method, the most commonly used method in guided-wave devices, is applied to optical filter design. The simulation result is compared with the published experimental result.

We present a novel wavelength tunable filter based on a resonant Mach-Zehnder interferometer using an electric thermo-optic phase shifter.

Optical backplanes are of increasing interest for commercial and military avionic processors, and for commercial supercomputers. Projected interconnection density limits of electrical interconnects are rapidly becoming a bottleneck, preventing optimal exploitation of electronic processor capability. A potential obstacle to the commercial development of optoelectronic interconnect components for backplane-based systems is the small market for such specialized technology. In order to ensure that a cost effective solution is available for backplane based systems, commonality with a higher volume application is required. We describe optical packaging techniques for board level waveguides and multichip modules which exploit materials, processes and equipment already in widespread use in the electronics industry, and which can also be applied to a wide range of optoelectronic modules for local area network and telecommunications applications. Rugged polyetherimide waveguides with losses of 0.24 dB/cm have been integrated with conventional circuit board materials, and optoelectronic die have been packaged in a multichip module process using equipment normally used for purely electronic packaging. Practical optical interfaces and connectors have been demonstrated for board-to-backplane and board-to-multichip module applications, and offer increased pincount over their electrical counterparts while retaining compatibility with existing electrical connector alignment and fabrication tolerances.

In the paper, an approach to adjustable directional single-mode optical fiber coupler is put forward properly, and the effect of coupling area on coupling ratio is given in detail. The effect is calculated theoretically. In the end, the coupler with a continuously variable coupling ratio has been fabricated.

Recent advances in optical devices, polymeric materials, and in the electronic MCM packaging and interconnect technologies could bring the cost of optical interconnect to a level affordable for module, board, and backplane level interconnect applications. Specifically, we discuss how the development in (1) vertical-cavity surface-emitting-laser devices, (2) multichip module packaging technologies, (3) optical polymers, and (4) adaptive interconnect can be applied to benefit optoelectronic packaging and interconnect. We show how these advancements will allow widely used planar processes and the already developed packaging technology in electronics to be applicable to optoelectronic packaging to reduce both recurring and nonrecurring engineering costs for this new technology insertion into computers and advanced electronic systems.

Light propagation loss of the micron size optical waveguides is found to be improved from 1.8 to 0.6 dB/cm by capping waveguides by Al film. Al micromirrors for changing the light propagation direction in the vertical and horizontal planes were fabricated. Various shapes of Al corner mirrors to change the light direction in the horizontal plane were investigated. The straight simple mirror at an angle of 45 degree(s) against the incident light has the largest reflectivity of 50%. Branched waveguides were also fabricated by using Al corner mirrors and resulted in the almost equal distribution of the light for three branches. Light emitting diodes (LEDs), micromirrors, waveguides and photodetectors have been integrated on a single chip and the signal transfer from the LED to the photodetector has been verified.

A new optical waveguide suitable for high-packing-density OEICs is proposed. The waveguides are embedded in trenches, with large depth/width ratios, in a silicon substrate. The spacing between the waveguides and their pitch were less than 2 micrometers and 4 micrometers , respectively. This structure enables ultra high density optical interconnections in a silicon substrate.

We present a novel surface-normal optical wavelength-division-demultiplexer (WDDM), working at 750, 770, 790, 810, 830 and 850 nm wavelengths. The device is based on an integration of a planar waveguide, a substrate waveguide and waveguide holograms. The unique optical in-plane to surface-normal conversion converts the difficult three spatial and three angular edge coupling problem into a planar surface one, resulting in a practical compact face-to-face packaging between the photodetector array and the demultiplexer. A six-channel wavelength-division-demultiplexer with equally spaced collinear surface-normal outputs are designed and demonstrated in a polymer-based planar waveguide in conjunction with holograms on a glass substrate.

In this paper, we report on a 5-channel wavelength division demultiplexer (WDDM) using substrate-guided waves in conjunction with a polymer-based Littrow hologram operating at 700, 710, 720, 730, and 740 nm, respectively. An average cross talk of -40 dB between adjacent channels is measured. The diffraction efficiencies of 69%, 78%, 83%, 77%, and 69% are both experimentally and theoretically confirmed for the five-channel WDDM device. Further study aiming at reducing the wavelength channel separation to 1 nm is also provided for future work. A device length of 6.4 cm corresponding to a propagation distance of 9.05 cm is required to achieve such a goal.

We have developed a hybrid optoelectronic circuit to demonstrate a free-space optical interconnect in a CMOS chip. Discrete GaAs-based optical devices are hybridly integrated with a 0.8 micrometers CMOS chip fabricated by a MOSIS foundry. The CMOS chip consists of two separate digital modules, an ALU and a ROM, communicating via a pair of optical interconnects. Each interconnect consists of a CMOS laser driver that converts full CMOS logic-level data into a suitable laser drive current, a laser-photodetector pair, and a CMOS transimpedance amplifier that converts a photocurrent from the photodetector into logic-level data. An on-chip clock is used to time the serialization and deserialization of 4-bit words of data across each interconnect at a data rate of 40 Mb/s. In order to account for limitations of the hybrid design as well as process variations, pads are provided for off-chip clock signals to override the built-in clock and therefore operate the interconnect at a transmission rate different from the design value. Each laser-photodetector pair is fabricated from a single laser structure epitaxially grown on semi-insulating GaAs substrate. Similar to a laser-photomonitor arrangement, a dry etch is used to divide the laser structure into a separate laser and photodiode. This device is then hybridly integrated with the CMOS chip to implement the proof-of-principle free-space optical interconnect. Experimental results for the optical elements and simulation results for the CMOS design are presented to demonstrate the operation of the chip.

Recent progress concerning GaAs on Si technology is discussed from the viewpoint of how to suppress the threading dislocation density in GaAs layers to the level of 10⁴cm² on the basis of recently obtained results. In particular, we consider the effects of new approaches for realizing two-dimensional growth, new materials of buffer layers and insertion layers, post-growth annealing, high energy ion implantation and the confinement of growth areas on the reduction of threading dislocation generation and propagation.

In this paper we demonstrate a novel Si wafer based optical clock distribution technique operating 1.3 micrometers and based on a central polygonal input coupling grating structure and surrounding rings of linear output coupling gratings. In this arrangement, both the central polygonal and linear output gratings have a period of 1 micrometers , allowing light to be efficiently coupled into and out of the Si wafer substrate mode in the surface normal direction. A double side polished Si wafer is used to limit the surface scattering losses as the signal travels through the bulk of the Si wafer. One of the major advantages of this technique is that, since the gratings can be written onto the Si surface using optical contact lithography and reactive ion etching, an array of grating shapes and depths can be selected to optimize the diffraction efficiency and focus the output beams onto the associated multi-chip module (MCM). This helps to reduce the optical power requirements that a future system would have and also allows for greater flexibility in system packaging design.

Al_xGa_1-xAs electro-optic (EO) zero-gap directional couplers (ZGDCs) offer orders of magnitude shorter device lengths than Al_xGa_1-xAs conventional directional couplers (CDCs). Due to the small EO activity of Al_xGa_1-xAs, however, the length of the Al_xGa_1-xAs ZGDC becomes voltage limit dependent. To operate at TTL levels, the interaction channel length of the active Al_xGa_1-xAs ZGDC needs to increase by 25 times over the optimum coupling length of the passive device. For the passive device, the coupling percentage can be easily controlled to within +/- 10% using standard lithographic and growth techniques demonstrating a fabrication tolerant device. The coupling percentage between channels in the longer active devices, however, is much more sensitive to the accuracy of the interaction length which, in turn, is controlled by the accuracy of processing and growth. If one could control the interaction length even to within 1 micrometers , holding the voltage independent phase change to within 1%, the coupling percentage could vary by as much as 45%. Because precise accuracy could not be achieved, the active Al_xGa_{1- x}As ZGDC fabricated for this experiment required a 30% higher switching voltage than optimum. Control of both material growth and fabrication processing is needed unless one is willing to continuously apply a voltage.

We have demonstrated a representative portion of an optical backplane using FET-SEED smart pixels and free-space optics to interconnect printed circuit boards (PCBs) in a two board, unidirectional link configuration. Four X four arrays of FET-SEED transceivers were designed, fabricated, and packaged at the PCB level. The optical interconnection was constructed using diffractive micro-optics, and custom optomechanics. The system was operated in two modes, one showing high data throughput, 50 MBit/sec, and the other demonstrating large connection densities, 2222 channel/cm².

We report for the first time a bi-directional optical backplane bus for a high performance system containing nine multi-chip module (MCM) boards. The backplane bus reported herein employs arrays of multiplexed polymer-based waveguide holograms in conjunction with a waveguiding plate within which 16 substrate guided waves for 72 (8 X 9) cascaded fanouts are generated. Data transfer of 1.2 Gbit/sec at 1.3 micrometers wavelength is demonstrated for a single bus line with 72 cascaded fanouts. Packaging-related issues such as transceiver size and misalignment are embarked upon to provide a reliable system with a wide bandwidth coverage. The backplane bus demonstrated is for general-purpose and, therefore, compatible with such IEEE standardized buses as VMEbus, Futurebus, and FASTBUS, and can function as a backplane bus in existing computing environments and significantly reduce the bottlenecks that accompany electrical interconnects.

We have designed a parallel processor system with hundreds of processors specific for Monte- Carlo analysis. This system has the ring-bus architecture. The performance of several Gflops is expected in this system according to the computer simulation. However, it was revealed that the data transfer speed of the bus has to be increased more dramatically in order to further increase the performance. Then, we propose introducing the optical interconnection into the parallel processor system to increase the data transfer speed of the buses. The double ring-bus architecture is employed in this new parallel processor system with optical interconnection. The free-space optical interconnection and the optical waveguide are used for the optical ring- bus. It was confirmed in simulation that the optical data transfer operation and the memory store operation into FIFO in the optical ring-bus interface unit can be successfully performed.

Optical interconnects have potential advantage over electrical methods at the backplane level. In this paper we present a free-space optical connection cube for backplane interconnect applications. The connection cube has a symmetric structure which reduces skew between boards. It can be expanded into a 3-dimensional configuration for parallel communication using vertical-cavity surface-emitting laser (VCSEL) and receiver arrays. Fan-out and fan-in of propagation beams for the connection cube are realized using volume holographic optical elements formed in dichromated gelatin (DCG) emulsion. A four-port communication system has been demonstrated using the connection cube and tested at 500 MHz. In this paper, advantages and detailed implementation of the free-space optical connection cube are presented. Design considerations for fan-out/in holographic gratings and alignment tolerances for the connection cube are discussed. Characteristics of the connection cube are also presented.

We simulate parallel and serial implementations of functions on VSTEP (vertical to surface transmission electro-photonic device) based digital optical computing architectures. Taking optical thyristors as representative devices, we find that intrinsic fan-in and fan-out losses negate many of the speed advantages of the parallel implementation. However, in the regime where VSTEP rise- and fall-times are of the same order as transcription time the parallel solution becomes more attractive.

The Parallel Optical Link Organization (POLO) is an industry consortium of Hewlett-Packard, Du Pont, AMP, University of Southern California, and SDL, supported by ARPA and will operate between August 1994 and August 1997. The POLO Consortium was formed to leverage the individual strengths of its members to develop low-cost, high-performance optical interconnect modules for applications in workstation clusters, high-speed switching systems, and multimedia. The goal of the program is to demonstrate the manufacturability of affordable optoelectronic transceiver modules and to provide application platforms that show a clear advantage over copper-wire interconnections. The technical objective of the program is to provide a 10 - 20 Gb/s parallel channel optical interconnect module with a projected manufacturing cost of about $10 per channel. In addition, the POLO Consortium provides a complete solution to the end user, including a programmable host interface module and software interface. The POLO Consortium has formed a User Group consisting of seven world-leading computer, telecommunication, and optoelectronic subsystem manufacturers. Regular meetings with the User Group are planned and at the first meeting, a full set of POLO Module specifications have been discussed and generated. The POLO Consortium will provide the User Group members with hardware for evaluation and feedback.

Realization of future applications indicated by roadmaps of present mainstream circuit and system technologies implies surmounting major practical barriers of higher power dissipation and density, higher densities of interchip and inter-module connections, and high-speed system operation. Both in combination or separately, optical interconnections and low-temperature system operation provide important system-level approaches to overcome these barriers. Emerging advanced electronic computing, information, and communication systems will increasingly seek to selectively use active cooling to alleviate expected higher power densities, stabilize temperature sensitive device operation (e.g. lasers in WDM systems), and achieve improved CMOS performance in advance of next generation design rule technology. Extension of active cooling to cryogenic temperatures, seen as a necessity for deep submicron and nanoscale device operation, then presents only an incremental system cost increase. Taken together, cryoelectronics and optical interconnections can be complimentary, providing together greater flexibility and opportunity for enhanced system performance than derivable individually. This paper explores the role of optical interconnections in actively cooled electronic systems with emphasis given to packaging and architecture implications as well as low temperature performance of optoelectronic devices.

Holographic optical switches are presented to implement Multistage Type 1 interconnection networks. These switches have unique features of compactness, lightweight and flexibility, which are suitable for system applications. The procedure to implement Multistage Type 1 network with our holographic optical switches has been discussed in detail. After optimum design, the unique features of compactness and flexibility of holographic optical switches efficiently eliminate all interconnection lines between switches. Not only the number of required components are reduced, but also the space of the system is significantly saved.

The complexity of optoelectronic systems is motivating the need for CAD tools which can simulate electronic and photonic device and circuit behaviors simultaneously and at multiple levels of abstraction. We describe such a tool, called AnaVHDL, which is being developed to concurrently simulate the behavior of optoelectronic systems consisting of digital, analog, and optical circuits. The approach is to extend the very high speed integrated circuit Hardware Description Language (VHDL) to describe the behavior of analog circuits and optical components, and to develop a simulation kernel which supports both discrete-event and continuous-mode simulation.

Optimized design for a bi-directional optical backplane bus, containing 72 (9 X 8) interconnects and employing arrays of multiplexed polymer-based waveguide holograms on a waveguiding plate, is presented in this paper. After an objective function for the system is established, the fan-out intensity fluctuations among all the different channels are minimized by solving a set of non-linear equations numerically. Particularly, the fan-out distribution for the case in which nine boards on one side of the optical bus are optimized. A global optimized diffraction efficiency distribution exits and the minimum fan-out intensity after optimization is 1.5% of the incident power.

A high-speed low-skew system clock distribution network on a multichip module (MCM) is considered in systems perspective using system bandwidth, allowable system switching energy, number of clock signal fanout nodes supported, and the flexibility of the network structure to accommodate placement and routing requirements of various integrated circuits on MCM. Electrical H-tree networks modeled as lossless transmission lines are designed and evaluated along with guided wave optical H-tree networks. System performance analysis of optical and electrical H-tree networks on MCM suggests that optical H-tree clock distribution network has a superior capability compared to the electrical one by providing larger bandwidth, larger fanout, smaller system switching energy, and a flexible network configuration.

Important properties of layouts are interconnection length, signal delay distribution, area (or space) requirements, power dissipation, bandwidth, reliability, etc. The usefulness of optoelectronic interconnections should be manifest in at least some of these properties. This paper is concerned with quantitatively modeling future optoelectronic systems, and estimating signal delay distribution. In this respect, it is an extension of previous work only considering average wire length. It leads to a characterization of how to use optoelectronic interconnections and how much is expected to be gained from it. As a direct result, we draw some preliminary conclusions on how to use optical interconnections in optoelectronic architectures.

The success of OEICs lies in the ability to fabricate complex electro-optic circuits with high yield and manufacturability. This paper reports on the design, fabrication, and testing of a high yield, 32 channel, fiber optic receiver array. The potential cost savings of the OEIC approach are discussed.

This paper discusses the sensitivity limitations of smart pixel optical receiver arrays fabricated in the GaAs FET-SEED technology. Four circuit topologies (high impedance clamped, resistive load partially clamped, differential transamp, and common gate) are compared. Simulated and experimental data are presented.

Low cost high performance optoelectronic components are critical for the success of fiber optic data links in applications such as chip-to-chip, board-to-board, or station-to-station interconnects. We present the current status of low-cost short wavelength (0.85 micrometers ) GaAs MSM/MESFET (metal-semiconductor-metal/metal semiconductor field effect transistor) monolithic opto-electronic integrated circuit (OEIC) receiver arrays. Four-channel OEIC receiver arrays have been designed, fabricated and tested. BERs of less than 10^-9 with 300 mV differential output voltages have been achieved at a bit-rate of 1 Gb/s with a -16 dBm 2⁷-1 pseudo-random bit sequence (PRBS) input optical signal.

A continuous-time shift-invariant cellular neural network (CNN) with hardware annealing capability, digitally programmable synaptic weights, and optical inputs/outputs has been developed. This electro-optical neurocomputing processor has great potential in solving many important scientific problems in signal processing and optimization. Advanced packaging for the proposed optoelectronic neurocomputing system is a thin-film silicon-substrate multichip module with flip-chip connection technologies. This paper presents two functional chips designed for the proposed electro-optical neurocomputing processor: a monolithic GaAs 2-D array of optical receivers, and a VLSI CMOS 2-D array of smart pixels based on the annealed CNN. Due to the multichip module integration of these chips in the same silicon substrate, a complete optoelectronics neurocomputing system can be realized in a very compact hardware.

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors complicates the use of feedback circuits. Thus feedback is generally not used in the front-end of our digital process CMOS receivers.

For large-volume optoelectronics applications, the low cost, manufacturability and reliability of silicon MOSFET technology are advantageous. In addition, silicon photodetectors operate quite efficiently at the 0.8 micrometers wavelength of economical AlGaAs light sources. In this letter, we report on a silicon-based monolithic optical receiver. A symmetric transimpedance preamplifier was designed and simulated for depletion-mode NMOS with L_gate equals 1 micrometers and V_T equals -0.1 V. The symmetric circuit provides insensitivity of dc bias point to FET threshold voltage deviation. The silicon photodiode is a planar p-i-n structure with a diameter of 20 micrometers . The fabrication of the integrated lightwave receiver was carried out on a nominally undoped p-type Si substrate. The p-i-n photodetector is fabricated directly on the high-resistivity substrate so that the thickness of the detector depletion layer is approximately equal to the optical absorption length of 0.8 micrometers light in silicon. A more heavily-doped p-well was formed for the NMOSFET fabrication. The silicon photodiodes have a dark current of 16 nA at 5 V, a break-down voltage of greater than 40 V, and a zero-bias capacitance of 40 fF. The external quantum efficiency of the photodiode at 870 nm is approximately 60% at 5 V without an AR coating, and the bandwidth of the device is approximately 1.5 GHz. Frequency response evaluation of the receiver indicates a bandwidth of 250 MHz with open eye diagrams demonstrated at 350 MBit/s.

Optical FET detectors were fabricated in both the MOSIS/Vitesse HGaAs₃ process and the AT&T field-effect-transistor-self-electro-optic effect device (FET-SEED) process. Typical responsivity is in the order of 1,000 A/W and response time in the order of 10 to 100 microsecond(s) ec at 50 nW optical input power. Such high gain detectors through commercially available industrial foundries are especially useful for optical neural network applications where high density integration requires very good uniformity and power dissipation limits the available optical power. The mechanism of such optical FET detectors are discussed.

We review our progress in the development of an optical interconnect technology consisting of optical and optoelectronic switches that integrate vertical-cavity surface-emitting lasers (VCSELs) with other photonic and electronic components, including heterojunction phototransistors (HPTs) and heterojunction bipolar transistors (HBTs). We describe a reconfigurable multi-access optical network architecture that allows many high speed electronic processors to simultaneously communicate with each other and with other shared resources, and for its implementation, an integrated optoelectronic switching technology that combines the functions of an optical transceiver and a spatial routing switch. The network provides parallel and dynamically reconfigurable optical interconnections between nodes, as well as optoelectronic interfaces to each processor. By converting data between the electrical and optical formats, these multi-functional switches can receive or transmit optical data, or to bypass and re-route it to another node. Optical switching has been demonstrated experimentally at a data rate of 200 Mb/s, and electrical-to-optical data conversion has been achieved at a data rate of > 500 Mb/s.

In this paper, a space-position-logic-encoding scheme is proposed, which not only makes best use of the convenience of binary logic operation, but is also suitable for the trinary property of modified signed-digit numbers. Based on the space-position-logic-encoding scheme, a fully parallel modified signed-digit adder and subtracter is built by use of optoelectronic switch and microstructure interconnect technologies. Thus an effective combination of a parallel algorithm and a parallel architecture is implemented. Finally, both simulation results and experimental results are provided.

This paper shows how short-range, free-space optical interconnects using holograms can solve optical routing problems within hermetic packages.