This PDF file contains the front matter associated with SPIE Proceedings Volume 6798, including the Title Page, Copyright information, Table of Contents, Introduction, and the Conference Committee listing.

Reduction of linear critical dimensions (CDs) beyond 45 nm would require significant increase of the complexity of pattern definition process. In this work, we discuss the key successor methodology to the current optical lithography, the Double Patterning Technique (DPT). We compare the complexity of CAD solutions, fab equipment, and wafer processing with its competitors, such as the nanoimprint (NIL) and the extreme UV (EUV) techniques. We also look ahead to the market availability for the product families enabled using the novel patterning solutions. DPT is often recognized as the most viable next generation lithography as it utilizes the existing equipment and processes and is considered a stop-gap solution before the advanced NIL or EUV equipment is developed. Using design for manufacturability (DfM) rules, DPT can drive the k1 factor down to 0.13. However, it faces a variety of challenges, from new mask overlay strategies, to layout pattern split, novel OPC, increased CD tolerances, new etch techniques, as well as long processing time, all of which compromise its return on investment (RoI). In contrast, it can be claimed e.g., that the RoI is the highest for the NIL but this technology bears significant risk. For all novel patterning techniques, the key questions remain: when and how should they be introduced, what is their long-term potential, when should they be replaced, and by what successor technology. We summarize the unpublished results of several panel discussions on DPT at the recent SPIE/BACUS conferences.

Adding dummy features (waffles) to drawn geometries of the circuit layout is a common practice to improve its manufacturability. As an example, local dummy pattern improves MOSFET line and space CD control by adjusting short range optical proximity and reducing the aggressiveness of its correction features (OPC) to widen the lithography process window. Another application of dummy pattern (waffles) is to globally equalize layout pattern density, to reduce long-range inter-layer dielectric (ILD) thickness variations after the CMP process and improve contact resistance uniformity over the die area. In this work, we discuss a novel type of dummy pattern with a mid-range interaction distance, to control the ILD composition driven by its deposition and etch process. This composition is reflected on sidewall spacers and depends on the topography of the underlying poly pattern. During contact etch, it impacts the etch rate of the ILD. As a result, the deposited W filling the damascene etched self-aligned trench contacts in the ILD may electrically short to the underlying gates in the areas of isolated poly. To mitigate the dependence of the ILD composition on poly pattern distribution, we proposed a special dummy feature generation with the interaction range defined by the ILD deposition and etch process. This helped equalize mid-range poly pattern density without disabling the routing capability with damascene trench contacts in the periphery which would have increased the layout footprint.

An 18.5 GHz divide-by-four digital frequency divider has been implemented in 0.25μm silicon-on-sapphire CMOS with a power dissipation of 41mW, supply voltage of 2.75V and size of 40×60μm. The design utilises two cascaded divide-by-two 6 transistor dividers. A buffer is used at the output of the first stage to minimise the capacitive load and restore the signal amplitude for the second stage. This significantly increases the operating speed of the circuit. An optimisation design method is proposed for sizing the transistors that uses the amplitude of the output voltage as a metric for the divider speed.

This work investigates the nature of the nonlinearities in an anti-parallel combination of Schottky diodes, which is often used as a frequency converting device or a mixer. An anti-parallel Schottky diode pair mixer requires only half the local oscillator frequency. The mixing terms of utmost importance are, the wanted fundamental frequency converted product, the unwanted third-order frequency converted product and the breakthrough of the local oscillator signal. This work aims to discover how the nonlinearities inside the mixer can affect the generation of unwanted products. Frequency upconversion measurements of an anti-parallel diode pair mixer, fabricated on WIN semiconductor's 0.15μm low-noise process have been used to extract a polynomial model of the mixer nonlinearities. The polynomial function representing nonlinear resistance contains only odd-power terms and a second polynomial function encapsulating capacitance and its asymmetry comprises of both even and odd-power terms. The coefficients of the model are extracted by fitting to measured amplitudes of the third-order mixing products and the local oscillator breakthrough over a range of the local oscillator drive powers, commonly encountered in practise. The model so extracted is validated by comparing its predictions with measured amplitudes of wanted and unwanted frequency products, as functions of local oscillator power at various local oscillator frequencies. The form of the polynomial model indicates the dominance of nonlinear resistance in the generation of the unwanted third-order mixing products. It also points to asymmetry of the capacitance-voltage characteristic as a possible reason behind unwanted local oscillator breakthrough in anti-parallel diode pair mixers.

Phased array antennas have a large number of civilian and military applications. In this paper we briefly review common approaches to an integrated implementation of radar and electronic warfare digital phase array module and highlight features that are common to both of these applications. Then we discuss how the promising features of the radio frequency integrated circuit (RFIC)-based technology can be utilized in building a transceiver module that meets the requirements of both radar and electronic warfare applications with minimum number of external components. This is achieved by researching the pros and cons of the different receiver architectures and their performance from the targeted applications point of view. Then, we survey current RFIC technologies and highlight the pros and cons of these technologies and how they impact the performance of the discussed receiver architectures.

This paper introduces an Ultra-Wideband (UWB) transceiver for in-vivo biotelemetry applications, especially for wireless endoscope. A system modeling, simulation and design trade-off analysis for an UWB impulse radio transceiver is presented that incorporates the human body attenuation effect, the IEEE 802.14a indoor channel model, and channel noise to determine an optimum architecture for the given applications. Based on the system simulation using Matlab, the severe effect from the human body attenuation has been identified and a non-coherent Transmit Reference (TR) Transceiver architecture with differential Binary Phase Shift Keying (DBPSK) modulation was selected as the best option for a communication link in biotelemetry applications. The transceiver consists of an all-digital transmitter with H-bridge output stage type of Pulse Generator (PG), wideband inductorless resistive shunt feedback Low Noise Amplifier (LNA) with thermal noise canceling, Gilbert mixer, Integrator, decision detector and Variable Delay Controller (VDC). The performance characteristics of the PG, LNA and mixer are presented by the circuit simulation results using 0.18μm digital CMOS technology.

For integrated circuit design up to 50GHz and beyond accurate models of the transistor access structures and intrinsic structures are necessary for prediction of circuit performance. The circuit design process relies on optimising transistor geometry parameters such as unit gate width, number of gates, number of vias and gate-to-gate spacing. So the relationship between electrical and thermal parasitic components in transistor access structures, and transistor geometry is important to understand when developing models for transistors of differing geometries. Current approaches to describing the geometric dependence of models are limited to empirical methods which only describe a finite set of geometries and only include unit gate width and number of gates as variables. A better understanding of the geometric dependence is seen as a way to provide scalable models that remain accurate for continuous variation of all geometric parameters. Understanding the distribution of parasitic elements between the manifold, the terminal fingers, and the reference plane discontinuities is an issue identified as important in this regard. Examination of dc characteristics and thermal images indicates that gate-to-gate thermal coupling and increased thermal conductance at the gate ends, affects the device total thermal conductance. Consequently, a distributed thermal model is proposed which accounts for these effects. This work is seen as a starting point for developing comprehensive scalable models that will allow RF circuit designers to optimise circuit performance parameters such as total die area, maximum output power, power-added-efficiency (PAE) and channel temperature/lifetime.

Advances in sensor technology and wireless communications have made networked micro-sensors possible, where each sensor individually gathers and transmits informations from the natural environment. Moreover, wireless sensor networks are emerging as a rich domain of active research involving hardware and system design, networking, distributed algorithms, security and data management. In this field, the development and implementation of suitable antennas is a key aspect for the performances of a wireless sensor network. This work aims to present an overview of the benefits and of the most recent advances in antenna technologies, investigating the possibility of integrating enhanced solutions in a large distributed wireless sensor network for the environmental monitoring. Different design techniques are here presented. These techniques have been developed by the authors and they have found applications in a number of fields: from array antennas, to reflectarrays, metamaterials, electromagnetic band gap and antenna miniaturization and integration. The considered radiating structures are divided into two groups: first, base station antennas for data gathering applications are analyzed and different solutions are proposed, in particular considering the compactness, the cost and ease of implementation of the directive structure needed for this kind of application. Second, miniaturized antennas are analyzed, in order to study the integrability and ease of manufacturing of sensor with advanced wireless capabilities. The design technique proposed in this work make use of enhanced global optimization procedures, i.e. evolutionary optimization algorithms, that have been suitably developed to perform the best choice of the most significant parameters in the design phase. These design techniques are finally applied to the design of the radiating structures described previously, in order to obtain suitable radiating structures for wireless sensor networks. The reported results show that the presented procedures can be reliable and effective for a wide spectrum of applications in electromagnetics and in other fields of scientific research.

Sensor networks are an emerging field of research which presents significant system challenges involving the use of large numbers of resource-constrained nodes operating essentially unattended and exposed to potential local communication failures. Current sensor networks address problems of meeting standards for accuracy and also delivering data from remote locations with an appropriate level of spatial and temporal resolution. Today advances in sensor technology, wireless communications and digital electronics make it possible to produce large amount of small-size, low-cost sensors which integrate together sensing, processing, and communication capabilities. The advantages are evident not only in the reduction of size, but also in the increase of functional performance and reliability, and a unit-cost reduction in mass production lines. In this work hybrid evolutionary algorithms are applied to optimize the design of cluster formation in wireless sensor networks, guaranteeing at the same time a full network connectivity and a minimum energy consumption. The proposed techniques have been tested in respect of the most known test functions with good results obtained in all the considered cases, especially for optimization of large domain objective functions. This feature makes these algorithms suitable for a wide range of applications, capable of outperforming classical procedures.

A prescaler is widely used in frequency synthesizers in order to handle channel selection. The division ratio has to be chosen carefully to achieve the desired frequency. In this paper, we present a 6 modulus prescaler in a 0.18 μm SiGe BiCMOS technology. The prescaler is part of a 60 GHz frequency synthesizer. In addition, we present a frequency planning for the 60 GHz frequency synthesizer. The prescaler employs an integer-N architecture. The circuit has a programmable divider with a division ratio of 7 and 8 and two counters to control the division ratio. The programmable divider utilizes ECL circuits, while the counters utilise CMOS circuits. Therefore an ECL-to-CMOS converter is used to bridge these two kinds of circuits. Simulation results show that the prescaler operates up to 4 GHz from a 1.8 V supply voltage.

The evolution of wide-bandgap semiconductor transistor technology is placed in historical context with other active device technologies. The relative rapidity of GaN transistor development is noted and is attributed to the great parallel activity in the lighting sector and the historical experience and business model from the III-V compound semiconductor sector. The physical performance expectations for wide-bandgap technologies such as Gallium-Nitride Field-Effect Transistors (GaN FETs) are reviewed. We present some device characteristics. Challenges met in characterising, and prospects for modeling GaN FETs are described. Reliability is identified as the final remaining hurdle facing would-be foundries. Evolutionary and unsurprising applications as well as novel and revolutionary applications are suggested. Novel applications include wholly monolithic switchmode power supplies, simplified tools for ablation and diathermy in tissue, and very wide dynamic range circuits for audio or low phase noise signal generation. We conclude that now is the time to embark on circuit design of MMICs in wide-bandgap technology. The potential for fabless design groups to capitalise upon design IP without strong geopraphic advantage is noted.

Device parameter variation across the product die and wafer compromises functionality, performance, and yield of integrated devices increasingly more as technology shrinks into the sub-100 nm range. Such variability is of special importance for System-on-Chip products, affecting e.g., frequency response of the analog/RF blocks. Variability reduction can be accomplished through tightening the manufacturing process, adding technology rules for manufacturability (Design-for-Manufacturability, DFM), or developing parameterized, correct by construction (CBC) design or layout (upstream approach). While so far the best option for variability reduction was to improve process capability without resticting product design (downstream approach), it may no longer be preferred due to the continuously increasing process cost driven by technology shrinks. In this work, we discuss a procedure to separate the variability for a 1D and 2D layout due to the lithography and other combined process effects. We then use this procedure to define design rules for analog/RF layout to minimize parametric variability at the minimal cost of the footprint. These rules can be subsequently used to create the CBC design and layout (upstream approach) such that the process window is traded for device footprint by the aggressiveness of the resolution enhancement techniques (e.g., optical proximity correction, OPC). Another option for variability reduction, the layout-time addition of design rules or OPC in response to the localized issues in a random layout (hot spots) causes reworks and delays and is not preferred.

There has been many low-swing on-chip interconnect signaling techniques introduced to tackle the problem of inverse-scaling effect of on-chip wires. This paper proposes a comparison framework using SPICE-based simulations on the 90nm technology node, which is needed to assess the effectiveness of a certain interconnect technique over the others with a high degree of objectiveness and accuracy. Two low-swing techniques are included in the comparison, i.e. conventional level converter (CLC) and current-mode signaling (CM). These techniques were chosen to represent different driver and receiver topologies, where CLC uses lower driver supply voltage, while CM has a low impedance termination at receiver end. In addition, an optimized full-swing repeater-based technique is included as a baseline for comparison. The main contribution of this paper is the identification of circuit and wire design parameters that affects performances the most, leading to a design guideline with reduced set of design variables for delay or energy optimization of each technique. A simplified repeater performance estimation technique considering ramp input signals is also proposed. Furthermore, trade-off between energy and delay using the optimization processes has been explored, resulting in a more objective comparison of different interconnect techniques in the power-delay space. Results show that optimized CLC (reduced voltage supply) repeaters can perform better in both terms of delay and power in its design performance range.

Field Effect Transistors exhibit a variety of complicated dynamic and nonlinear interactions that affect millimetre-wave devices used for telecommunications. The dynamics include self heating, bias dependent change in trapped charge, and variations due to impact ionization. These are feedback mechanisms that contribute to intermodulation as a memory effect does. A FET is better viewed as a nonlinear system with feedback, bias dependent rates, and high-order nonlinear conductance and charge storage with specific terminal to terminal interaction. Identifying and characterizing FET dynamics and linearity is a key step in the design process. Extraction of true intrinsic characteristics is an important first step to understanding the physics of trapping and heating within the device. Standard measurement techniques tend to derive access networks with an emphasis on scaling with layout geometry. The intrinsic device is then modelled as whatever is left after de-embedding the measurements. As such, the intrinsic model exhibits significant frequency dispersions and behaviour that is not easily related to the operation of the transistor. A correct determination of the access network reveals that the dispersions within the intrinsic data are related to physical process, such as heating and trapping. Recent work has been carried out to accurately implement trapping within a circuit simulator. This is key to correct prediction of intermodulation and bias dependence effects generated by a FET. It is shown that heating significantly affects trapping and is an important factor in the transient rate dependence of the characteristics. The implementation of trapping within a circuit model, and its consequences on linearity are explored.

This paper introduces a new input pattern dependent model for total static leakage estimation in ultra deep submicron processes. The model integrates gate tunnelling leakage, gate induced drain leakage (GIDL) and subthreshold leakage into a single leakage estimation framework. Subthreshold estimation is facilitated through the analytical estimation of nodal voltages between OFF transistors, while gate tunnelling leakage and GIDL are calculated based on simplified versions of their respective BSIM4 equations. The framework deals with all input patterns and accommodates scenarios where the various leakage currents interact. Similar approaches in the literature are either based on a look up table approach, and do not accommodate transistor stacks with varying widths, or are highly experimental and require a detailed knowledge of the transistor device physics. Several approaches also exist for modeling either subthreshold leakage or gate tunnelling leakage separately. Even those approaches use a lookup table approach, fix all widths in a transistor stack and/or limit the stack size to 2-3 transistors. The model proposed in this paper is tractable and almost completely analytical. It is capable of accommodating stacks with up to 4 transistors with varying transistor widths. A stack estimator function based on this model was coded in MatLab for the 65nm, 45nm and 32nm PTM process technologies. Compared with SPICE simulations the model exhibited an average error of 1.29%, 2.79%, 7.57% and 11.42% for stack sizes of 1, 2, 3 and 4 respectively across all three technologies. The model also exhibits significant runtime savings when compared with SPICE.

This paper presents a novel approach for technology partitioning in a library free paradigm based on the use of virtual cells. Previous methods for library free logic partitioning rely on creating the largest possible partitions from a user defined criteria, predominately the stack length of the transistor level implementation. However, these methods can cause conflicting structures, defying the AND-OR-INVERT (AOI) and OR-AND-INVERT (OAI) representations that are used as templates for the virtual cells. The Complementary Logic Partitioning (CLP) algorithm, defines a partition as consisting of only two hierarchical levels of complementary nodes (AND and OR), as well as using the logical effort model for the migration of inputs to optimize the partitions to meet both the user defined limiting criteria and minimize the delay of the inputs. The CLP algorithm is compared against Synopsys' Design Compiler using Artisan standard cell library for a set of MCNC '91 benchmarks. Preliminary simulation results based on TSMC's 0.18 micron CMOS technology, show a reduction of more than 50% in the critical path delay can be achieved with CLP.

Nonlinear behavior of a capacitively driven and sensed micromechanical free-free beam resonator is characterized, modeled and experimentally verified in this paper. Both the mechanical and electrostatic nonlinear effects are included in the resonator model. Instead of using the FEM tools which introduces uncertainties to the simulation process, an alternative semi-analytic method is proposed to identify the resonator parameters from just a few preliminary testing results. A 615kHz free-free beam resonator was designed, fabricated and studied. From the experimental results, it is observed that the nonlinear effects in the free-free beam always shift the resonant peak of the beam to a higher frequency under nonlinear vibration. In order to validate the proposed modeling approach, a nonlinear model was constructed based on the experimentally extracted parameters and numerically solved in MATLAB. The simulation results were compared with the experimental data, showing that the measured large-signal frequency domain response can be accurately reproduced by simulation. Although this work focused on the free-free beam resonator, the proposed modeling approach is not specific to flexural designs, but is valid for all types of electrostatic resonators. Such a method to predict nonlinear effects of microresonators will be especially useful for MEMS oscillator and filter applications.

This paper presents the results of our work in building a finite element based numerical model, to study and understand the actuation characteristics of gels especially in response to the changes in pH, temperature and electrical potential. Steady state behavior of the gel is considered initially within an overall model based on 'equilibrium mechanical condition' with buffer and fixed ion concentrations as the most affecting parametric variables. The finite element analysis was carried out using commercially available multi-physics software, 'COMSOL'. This simulation used the variables fixed charge density, pH (2-12), buffer solution ionic concentration (2- 10 mM) and electric potential (0 to 2 V). The variation in gel deformation characteristics with respect to temperature and applied electrostatic potential are presented. The typical dimensions of the actuator considered are 1 mm × 3 mm. The gel deformation or displacement with varying length to width ratio and applied potential is also described. A detailed analysis of these results is discussed in this paper.

In this paper we present a CAD tool capable of generating a variety of parallel prefix adders described in the VHDL language. The VHDL code generated by the tool is synthesizable and the resulting adders can be used as design components in an automatic or semi-custom design flow. In its current version the tool is able to generate arbitrary bit-size prefix adders of the following types: Sklansky, Ladner-Fischer, Kogge-Stone, Han-Carlson, Brent-Kung and Knowles.

A novel and simple circuit implementation of trap centres in GaAs and GaN HEMTs, MESFETs and HFETs is presented. When included in transistor models it explains the potential-dependent time constants seen in the circuit manifestations of charge trapping, being gate lag and drain overshoot. The implementation is suitable for both time- and harmonic-domain simulations. The trap-centre model is based on Shockley-Read-Hall (SRH)¹ statistics of the trapping process. It also accommodates carrier injection from other important device effects, such as impact ionization and light sensitivity. In the model, the ionization charge of the trap centre is represented by the charge in a capacitor. The potential across the capacitor is proportional to the potential across the region of the trap centre in the semiconductor. It is positive or negative depending on the polarity of the ionization charge - electrons or holes. When included in a transistor model, this potential is added to the gate potential that controls the drain-current description. The capacitor is charged or discharged by two opposing currents that are functions of the ionization potential and temperature: one models charge emission; and the other, which is also controlled by an external potential and injected current, models charge capture. The external potential is typically a linear function of a transistor's terminal potentials. The injection current can model charge generated by light or by holes from impact ionization. The four parameters for the model are simply the signed potential of the trap centre when fully ionized, the time constant for charge emission at a specific temperature, the injection-current sensitivity, and the activation energy of the emission process. The latter is used to predict the temperature dependence of the emission rate. The capture rate is determined within the model by an exponential function of the external potential that controls capture. Thus the model elegantly predicts asymmetry between trap charging and discharging rates. The model accounts for variation in emission and capture rates with temperature, which is shown to vary significantly over typical transistor operating ranges.

When the design engineers discuss the new concept of the embedded electronic packaging, there are a lot of kinds of materials on the list, the resins, silicones, and so on. Therefore, it is very important to study and understand the basic effect of the new materials on the important components of their products at the early stage. In the study, the authors used simulation approach to investigate several different concepts of the embed package, and the focus is the effect of the important components. Based upon the analytical results, the advantage and demerit of each concept were discussed.

Machine vision has long been an important topic of study ever since electronic image sensors were developed. One of the main problems in machine vision is achieving a reliable estimate of velocity for objects of interest within the sensor's visual field. Traditionally, estimating velocity based on full correlations has been impractical due to hefty computational requirements. As a result, most vision chips have adopted simplified models, such as the Reichardt correlator. With advances in digital microelectronics and mixed signal techniques, there appears to be an opportunity for the development of a velocity estimation chip which performs full correlation-based velocity estimates. This paper presents an algorithmic investigation into the feasibility of such a scheme. In our proposed approach, the image information is encoded using a non-linear, over-sampled single-bit representation. Correlation computations are performed on this over-sampled signal, with the reduced precision of the single-bit representation providing a trade-off against the increased sampling rate. The quality of the achievable velocity estimates are evaluated against correlators operating on conventional image sensors, using rotated natural panoramic image sequences as input. Preliminary results suggest the proposed scheme to provide a reasonable estimations of velocity, with the potential advantage of requiring very simple logical circuits.

The past few years have seen a significant shift in passive RFID tags performance and advancement. RFID standards have evolved, as users of technology proliferated across several industries. Innovation in the readers, however, has been very slow. But all that can change by using software defined RFID readers. Being software based means that radios, terminals and networks are becoming reconfigurable and programmable. Research in software and cognitive radios is bringing rapid development. Even though these concepts are under active research, many challenges remain in making this vision a reality. In this work we study several aspects of a cognitive software based RFID reader, implementing a practical standards-compliant RFID reader using FPGA and off-the-shelf RF components. In this paper experimentation, implementation and theoretical work is described.

There is a demand for more efficient sources of electromagnetic radiation in the terahertz (THz, 10¹² Hz) frequency region. One common method of generating THz-frequency radiation is to direct fs pulses of near-infrared laser radiation onto a material which then re-radiates. This approach permits coherent pulses of THz radiation to be produced which, for example, may be used for time-domain spectroscopy (TDS). There are three principal mechanisms by which THz radiation is generated under the stimulus of ultra-short pulses: optical rectification (OR) in electro-optic materials, photoconductivity (PC) from materials with suitable electrodes, and surface-field (SF) effects in other cases. The III-V compound semiconductor GaAs doped with the acceptor impurity Be produces relatively small amounts of THz radiation via the OR and SF mechanisms, but relatively large amounts via the PC mechanism. We have studied the PC emission of THz radiation from layers of GaAs(Be) grown epitaxially on GaAs substrates. The THz power generated depends on the bias applied to the electrodes approximately quadratically. This is typical of the PC mechanism. The dependence of the THz power on the power of the pump beam is approximately linear. In general, the THz generated tends to decrease as the doping level increases. If the doping level exceeds the Mott limit and the material becomes highly conductive then the photoconductivity and consequently the THz production are quenched.

Wireless acoustic communications methods have been demonstrated. These include both electro-acoustic and acoustooptic communications. The communications methods are intended for use by autonomous robotic agents in the Non- Destructive Evaluation (NDE) of structures containing a distributed acoustic emission sensor network. The acoustic emission sensors can be based on either piezoelectric or optical fibre sensors. The communications channel comprises of a piezoelectric transducer as the transmitter, an aluminium panel as the transmission medium, and either a second piezoelectric transducer or an optical fibre sensor as the receiver. Distributed acoustic emission sensors are used in Structural Health Monitoring (SHM) for the detection of impacts and/or strain, in real time. Secondary damage may result from the initial impact or strain. This damage may include surface pitting, erosion, or cracking. These types of secondary damage may not be detectable, and hence may not be able to be monitored by the SHM system; specifically in optical fibre based sensing systems. The integration of NDE by robotic agents into a SHM sensor network enables the detection and monitoring of a wider variety of damage. Acoustic communication represents a wireless communication method that does not require any additional hardware, as piezoelectric transducers are commonly used in the NDE of materials. Various modulation methods were investigated for the communications channel. These include Amplitude Shift Keying (ASK), Frequency Shift Keying (FSK), and Phase Shift Keying (PSK). Successful communication was achieved using both the piezoelectric and optical fibre receivers. The optical fibre sensor used was a Fibre Bragg Grating (FBG).

In this paper, gate-induced pentacene semiconductor strain sensors based on hybrid-gate dielectrics using poly-vinylphenol (PVP) and high-K inorganic, Ta₂O₅ are fabricated on flexible substrates, polyethylene naphthalate (PEN). The Ta₂O₅ gate dielectric layer is combined with a thin PVP layer to obtain very smooth and hydrophobic surfaces which improve the molecular structures of pentacene films. The PVP-Ta₂O₅ hybrid-gate dielectric films exhibit a high dielectric capacitance and low leakage current. The sensors adopting thin film transistor (TFT)-like structures show a significantly reduced operating voltage (~6V), and good device characteristics with a field-effect mobility of 1.89 cm²/V•s, a threshold voltage of -0.5 V, and an on/off ratio of 10³. The strain sensor, one of the practical applications in large-area organic electronics, was characterized with different bending radii of 50, 40, 30, and 20 mm. The sensor output signals were significantly improved with low-operating voltages.

Due to the development of new technologies, more and more complex MEMS applications can be realized. Especially electromagnetic micro actuators have reached a growing interest in micro technology in addition to commercial applications during the last years. Their basic construction exists of electric conductors and coil systems as well as of soft-magnetic and/or hard-magnetic materials that were fabricated in additive technology via UV-depth lithography and electroplating. For UV-depth lithography, photo resists like Epon SU-8, AZ9260, Intervia-3D-N and CAR44 were applied and optimized. Layer thickness up to 1 mm and aspect ratios over 60 were achieved. Special micro composites were developed. This allowed the fabrication of micro magnets with arbitrary shape and properties, revealing a complete compatibility to existing process chains. With these potential technologies, several complex 3-D micro actuators like micro motors and micro robots were developed and successfully tested. These developments include in detail: linear and rotatory reluctance micro stepper motors with compensated attraction force as well as a special "Lorentz force actuator", which was used for micro robots and micro motors. The micro robots were deployed for assembling and for micro-/nano positioning. Furthermore "plunger coil actuators" were realized based on a voice coil principle, which were used e.g. for a micro switch or a micro mirror. Moreover, rotatory synchronous motors were developed and successfully tested. All these devices have been realized by outstanding fabrication technologies and can be used for a wide range of applications.

Wafer level packaging is important for MEMS to protect micromechanical structures from mechanical stresses, dusts, humidity and other contaminations. Thru Si Via etching is Key technology. In the case of ±5% of CD shift value in the etching conditions for TSV processing, the amount of volume change of thru hole in a wafer is generated about 20% at the maximum. As a result, dispersion of the density and width of Cu wiring occurs, and it leads to the increase in an error due to the margin fall of a circuit. Therefore, not only etching depth uniformity but also uniform control of CD shift is very important for TSV etching. We developed a novel deep silicone etcher "NLD-Si". This equipment has introduced the sputter system into the passivation process in the vertical etching. As a result of film coverage being controllable by optimization of this sputter condition, advanced anisotropic etching was achieved. Furthermore, by using the sputter and NLD (Magnetic Neutral Loop Discharge) plasma uniformity control system at 8 in. wafer, ±1.62% of the anisotropic etch uniformity was achieved in diameter 0.8um via and aspect ratio is above 10.

The earlier astable multivibrator formed by silicon tunnel diode has the disadvantage of low speed and non-modulation. NDRHBT is a novel type of HBT with NDR characteristics and high speed. Its NDR characteristics can be modulated by the base voltage V_BE or base current I_B. So the astable multivibrator formed by NDRHBT has the advantage of high speed, high frequency, bistability, and frequency modulation by V_BE or I_B. Thus, it can be applied widely in high frequency oscillation circuits and high speed-digital circuits. In this paper, it is demonstrated that the frequency of the astable multivibrator can be modulated by base voltage V_BE. The experimental result shows that the frequency of time interval between two adjacent pulses f₁ varies from 7×10⁴Hz down to 2.5×10⁴Hz as V_BE changes from 4.5V to 6.5V and exhibits near a linear relationship. So it is can be used as an efficient voltage controlled frequency modulator for pulse signal in high speed digital circuits.

This work compares classification results of lactose, mandelic acid and dl-mandelic acid, obtained on the basis of their respective THz transients. The performance of three different pre-processing algorithms applied to the time-domain signatures obtained using a THz-transient spectrometer are contrasted by evaluating the classifier performance. A range of amplitudes of zero-mean white Gaussian noise are used to artificially degrade the signal-to-noise ratio of the time-domain signatures to generate the data sets that are presented to the classifier for both learning and validation purposes. This gradual degradation of interferograms by increasing the noise level is equivalent to performing measurements assuming a reduced integration time. Three signal processing algorithms were adopted for the evaluation of the complex insertion loss function of the samples under study; a) standard evaluation by ratioing the sample with the background spectra, b) a subspace identification algorithm and c) a novel wavelet-packet identification procedure. Within class and between class dispersion metrics are adopted for the three data sets. A discrimination metric evaluates how well the three classes can be distinguished within the frequency range 0.1 - 1.0 THz using the above algorithms.

The design of a motion detector as a robust velocity estimator for real-world applications is massively challenging. Apart from accuracy and reliability it is difficult to achieve operation in real-time. The design should also be small, low cost, low powered and easily integratible. The Reichardt Correlator is often chosen for velocity estimation due to its accuracy. Unfortunately, the Reichardt Correlator is not a robust estimator of velocity as its output depends on specific aspects of stimuli such as the brightness and spatial frequency. In the literature, robustness is usually achieved through a highly elaborated Reichardt Correlator. Many of these elaborations are difficult to implement in VLSI and they impact significantly on the ability of the motion detector to operate in real-time. Our simple hardware approach is an analog/digital hybrid in VLSI that utilizes a simple front-end design for the pre-processing of input and does not require a specialised VLSI process. The minimized analog parts improve the reliability and low power consumption of the system. The proposed digital part is simple, compact and technology independent. Simulations verify that this design is capable of significantly reducing the dependency of the motion detection model on image brightness.

A single-FET active balun has been developed with a phase imbalance of less than ±1.5° and amplitude imbalance less than ±0.6dB from 4 to 8 GHz using 0.25μm silicon-on-sapphire CMOS. The source terminal of the transistor has been compensated with a shunt capacitance to ground and increased value for the source resistance. The compensation network has improved the phase imbalance by 29° at 8 GHz. The circuit dissipates 15mW and is 260×300μm including AC coupling capacitors.

We propose a high performance ROIC for IR image sensor applications. Because a micro bolometer image sensor, used in an IR image sensor, is made by a MEMS process, the resistance of bolometers by each process does not appear same value under same IR energy incident condition. This resistance variation generates a different output signal for same input by each chip. Instead of a single input mode, we used a differential input mode to the proposed ROIC and thus, a new circuit structure that has high immunity to the process variations of micro bolometer was invented. This result is due to the characteristics of the differential input mode that suppress the commonly appeared error and amplify the differentially applied signal. Using results from a computer simulation, improvement such as that the effect of the process error on the bolometer's resistance was decreased 10 ~ 12% without an additional compensation circuit was found. Moreover we had analyzed the results by numerical methods and found that it is possible to control the gain and compensation ability by design the capacitors of the integrator appropriately. A full chip including a ROIC and a micro bolometer with 16 X 16 cell arrays was designed and implemented in standard 0.25um CMOS process.

The lateral PIN photodiode (LPP) can be fabricated with ease using standard CMOS techniques such as diffusion or ion implantation to form the p+ and n+ wells in the absorbing layer. A novel diffusion-based three-dimensional LPP was modeled utilizing In_0.53Ga_0.47As as the absorbing layer. Interdigitated electrode structures were used to obtain responsivity of ~0.5-0.6 A/W and -3dB frequency of ~14-15 GHz at a wavelength of 1550 nm, bias voltage of 5V and optical power of 10 Wcm^-2. The modeled device is able to cater for 10 Gbit/s optical communication networks.

This paper investigates up/down conversion asymmetry in intermodulation distortion observed in measurements of resistive FET mixers. Symmetric behaviour is intuitively expected of such a topology, so a first principle analysis is carried out to determine the responsible mechanism. Previous analysis of up/down conversion asymmetry has focused on conversion gain in diode based mixers, whereas the effects investigated in this paper are for mixers with symmetry in this aspect. The aim is to fully understand the intermodulation mechanism, so that performance can be enhanced. The approach taken is to consider the mixer as a two-port nonlinear element driven by multiple frequency sources. Mixing performance then becomes a function of the relative frequencies and amplitudes, which is related to the mode of operation as an up or down converter. This investigation is performed with FET models of increasing complexity and physical accuracy. In this manner the effect on intermodulation and other mixer performance parameters can be isolated to those differences introduced with each model change such as the effect of adding higher order even/odd terms to the drain or gate non-linear model independently. The result is an understanding into the FET properties that contribute to intermodulation distortion. This knowledge is useful to designers as it allows educated modifications to mixer topology to obtain improved linearity. Results also give the ability to minimize the asymmetry, reducing the design cost involved in producing a separate solution for each mode. These results can also be used to guide modification of the physical structure of a FET for mixer applications.

Mechanical and thermodynamic measurements are reported for specimens spark plasma sintered from tungsten nano-powder. A maximum Vickers hardness of 3.31±0.03 GPa, at a relative density of 0.98 was achieved at sintering temperature of 1,800°C and above. This corresponds to the value of hardness for bulk tungsten. Grain size analysis indicated a grain growth activation energy of 160±10% KJ/mol. Sintering temperatures were found to be as much as 270°C lower than previously reported. During the Spark Plasma Sintering (SPS), a reduction in the amount of tungsten oxide was observed, especially at temperatures above 1,500°C. A number of mechanisms are thought to be responsible including the SPS induced decomposition of the oxide into metallic tungsten.

The mechanical properties of silicon nitride films are investigated. Freestanding films of silicon nitride are fabricated using the MEMS technique. The films were deposited onto (100) silicon wafers by LPCVD (Low Pressure Chemical Vapor Deposition). Square and rectangular membranes are made by anisotropic etching of the silicon substrates. Then the bulge test for silicon nitride film was carried out. The thickness of specimens was 0.5, 0.75 and 1μm respectively. By testing both square and rectangular membranes, the reliability and valiant-ness of bulge test with regard to the shape of specimens was investigated. Also considering residual stress in the films, one can evaluate the Young's modulus from experimental load-deflection curves. Young's modulus of the silicon nitride films was about 232GPa. The residual stress is below 100MPa.

In this work we investigate the use of polymer materials as a basis for fabrication of a novel type of pressure sensors for use in medical diagnostics. Experience with solid-state micro-electromechanical systems (MEMS) sensors has proved them to provide a number of desirable characteristics in sensory applications, including miniaturization and low production cost. However, owing to their rigidity, and bio-incompatibility, the solid-state sensors are not ideally suited for applications in biomedical implants and in-vivo diagnostics. They often require extra encapsulation protection, and thus diminishing their sensitivity and selectivity. Polymeric materials such as polyimide have been for a number of years utilized to manufacture flexible printed circuit board (FPCB) and membrane switches used in computer keyboards. Related work on polymer electronics has shown feasible the fabrication of micro sensors using polymer materials. In this paper we show that combining the polymer thick-film (PTF) technology with the MEMS micromachining process yields a workable platform for the realization of a flexible sensor for pressure measurements. We will show simulation results that establish the validity of the model and which will confirm the promise that these devices hold for future biomedical instrumentations. Recent sensor research by another group demonstrated a multi-model tactile sensor which consists of hardness, temperature, and thermal conductivity sensing features, all combined and built on a polymer substrate [1] and [2]. Advantages of using polymer materials include flexibility, biocompatibility, robust characteristics, reduced fabrication complexity and reduced production costs, as well as the use of environmentally friendly manufacturing.

All optical switches have been used with measured success in response to a high demand in all optical networks, and a dramatic increase in the Internet and communication needs over the last decade. The wavelength-selective switch is the mechanism used in various switching applications. MEMS-based wavelength-selective switches (WSS) are the most promising technology to bring all-optical switches into wide implementation by providing reasonable cost, excellent performance, and most reliable use of micro-electromechanical systems (MEMS) technology. Optical-MEMS devices, often referred to as micro-opto-electromechanical systems or MOEMS; have been used successfully in optical network systems and particularly in switching devices such as waveguide and free-space switches. Free-space switching devices are more popular than waveguide switches, because they offer faster switching time and are more scalable. 1D MEMS-based WSSs, using free-space approach, require the use of integrated multiplexer/de-multiplexer and micro-mirror arrays for their operations [1, 2]. The switching time depends primarily on the time it takes for the scanning micro-mirrors to steer de-multiplexed beams to the desired output ports. This is due to the fact that the mirrors are the main inertial components in free-space switching systems. Grating Light Modulators (GLM) were introduced a decade ago for use in diffraction optics. Research has begun to investigate their use in communication optics. Unlike other 1D MEMS-based WSS, GLM promises to offer very low loss for the whole system and fast switching time of as low as 20 ns with no integrated micro-mirrors [3-5]. We propose the development of a switching system incorporating a GLM as the central unit acting as both de-multiplexer and switching device in one spot, and which does not require any moving micro-mirror arrays. Therefore, the switching time is entirely dependent on the GLM device which is relatively fast. GLMs use diffraction principles to de-multiplex a WDM signal with a square-well grating-like deformation when suitable voltages are applied to the device to perform switching between 'ON' and 'OFF' states. We review the fundamental of GLM and its operation and showcase our proposed configuration that will confirm the promise that GLMs hold for future wavelength switching applications.

CMOS vision chips for edge detection based on a resistive circuit have recently been developed. These chips help develop neuromorphic systems with a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends dominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the MOSFET for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160×120 CMOS vision chips have been fabricated by using a standard CMOS technology. The experimental results have been nicely matched with our prediction.

Silicon carbide (SiC) single crystals have been used as the substrates of a new generation of wide band-gap semiconductors due to their unparalleled combination of high breakdown voltage, extreme temperature tolerance, mobility and radiation hardness. For their applications, the SiC substrates need to be machined with nanometric surface quality as well as high form accuracy. However, the superior properties of the materials render their machinability extremely difficult. In this paper, we report the form error and surface roughness of the 6H-SiC (0001) substrate mechanically polished using 3 μm diamond powders in two different polishing processes. One process was concentrated-load polishing; the other was surface polishing. The polished surfaces were evaluated using white light interferometry and atomic force microscopy (AFM) for assessment of two- and three-dimensional topographies including form error and surface roughness. We found that a large form error was produced on the 6H-SiC (0001) substrate in the concentrated-load polishing. The root-mean-square (RMS) surface roughness of approximately 4 nm was resulted. Surface polishing of the 6H-SiC (0001) substrate remarkably improved form accuracy. The RMS surface roughness of approximately 2.5 nm was obtained.