Cel Resist Processing For Submicron CMOS And Bipolar Circuits

K. E. Petrillo; M. J. Smyth; D. R. Hall

doi:10.1117/12.968305

1 January 1988 Cel Resist Processing For Submicron CMOS And Bipolar Circuits

K. E. Petrillo, M. J. Smyth, D. R. Hall

Proceedings Volume 0920, Advances in Resist Technology and Processing V; (1988) https://doi.org/10.1117/12.968305
Event: Santa Clara Symposium on Microlithography, 1988, Santa Clara, CA, United States

Abstract

A contrast enhancement layer (CEL) process was developed with a commercially available contrast enhancement material on top of a novalac-based resist for use on a 5X i-line stepper. This process extends the resolution capabilities to the 0.5μm range while maintaining vertical resist profiles at all measured dimensions up to 2μm. In comparison to an image reversal process capable of achieving submicron resolution, the CEL process technique has increased resolution, improved control of linewidth bias and exposure latitude, and has an exposure time of one half that of the image reversal process, increasing the throughput in the exposure tool. The CEL process was developed for both submicron CMOS and bipolar circuits. It was used at the emitter level of the bipolar process to pattern emitters of varying sizes down to 0.6μm by 4μm with the required vertical resist profile. The poly level of the submicron CMOS work was patterned using the CEL process with poly gates as small as 0.5μm. It has also been used at the contact hole level of the CMOS work, replacing a two layer resist system. An analysis of optical linewidth measurements from both the CMOS and bipolar circuits will be given.

Citation Download Citation

K. E. Petrillo, M. J. Smyth, and D. R. Hall "Cel Resist Processing For Submicron CMOS And Bipolar Circuits", Proc. SPIE 0920, Advances in Resist Technology and Processing V, (1 January 1988); https://doi.org/10.1117/12.968305

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