User-friendly design approach for analog layout design

Yongfu Li; Zhao Chuan Lee; Vikas Tripathi; Valerio Perez; Yoong Seang Ong; Chiu Wing Hui

doi:10.1117/12.2258203

28 March 2017 User-friendly design approach for analog layout design

Yongfu Li, Zhao Chuan Lee, Vikas Tripathi, Valerio Perez, Yoong Seang Ong, Chiu Wing Hui

Proceedings Volume 10148, Design-Process-Technology Co-optimization for Manufacturability XI; 1014814 (2017) https://doi.org/10.1117/12.2258203
Event: SPIE Advanced Lithography, 2017, San Jose, California, United States

Abstract

Analog circuits are sensitives to the changes in the layout environment conditions, manufacturing processes, and variations. This paper presents analog verification flow with five types of analogfocused layout constraint checks to assist engineers in identifying any potential device mismatch and layout drawing mistakes. Compared to several solutions, our approach only requires layout design, which is sufficient to recognize all the matched devices. Our approach simplifies the data preparation and allows seamless integration into the layout environment with minimum disruption to the custom layout flow. Our user-friendly analog verification flow provides the engineer with more confident with their layouts quality.

Citation Download Citation

Yongfu Li, Zhao Chuan Lee, Vikas Tripathi, Valerio Perez, Yoong Seang Ong, and Chiu Wing Hui "User-friendly design approach for analog layout design", Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014814 (28 March 2017); https://doi.org/10.1117/12.2258203

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