Wafer-level inspection platform on high-volume photonic integrated circuits for drastic reduction of testing time

Toru Miura; Yoshiho Maeda; Shinji Matsuo; Hiroshi Fukuda

doi:10.1117/12.2527382

21 June 2019 Wafer-level inspection platform on high-volume photonic integrated circuits for drastic reduction of testing time

Toru Miura, Yoshiho Maeda, Shinji Matsuo, Hiroshi Fukuda

Author Affiliations +

Proceedings Volume 11056, Optical Measurement Systems for Industrial Inspection XI; 110562R (2019) https://doi.org/10.1117/12.2527382
Event: SPIE Optical Metrology, 2019, Munich, Germany

Abstract

We describe a wafer prober integrated with an optical probe for wafer-level inspection of photonic integrated circuits. The design of the electric and photonic circuit was optimized for wafer-level inspection. The customized prober and circuit design enabled us to perform high-volume and high-speed inspection of over 400 elements, and sufficiently reliable results were obtained. It took about 10 sec. to evaluate the propagation loss of an element. This technology will be a key to reducing the costs of photonic devices.

Citation Download Citation

Toru Miura, Yoshiho Maeda, Shinji Matsuo, and Hiroshi Fukuda "Wafer-level inspection platform on high-volume photonic integrated circuits for drastic reduction of testing time", Proc. SPIE 11056, Optical Measurement Systems for Industrial Inspection XI, 110562R (21 June 2019); https://doi.org/10.1117/12.2527382

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