Paper
23 March 2020 Advanced high order field-to-field modeling for wafer edge control
Boris Habets, Stefan Buhl, Wan-Soo Kim, Patrick Lomtscher, Holger Bald, Tobias Hoeer
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Abstract
In leading-edge lithography, field-by-field corrections, also known as corrections per exposure, are well established. Many manufacturers use a combination of the traditional higher order wafer and intrafield polynomial corrections, combined with linear field-by-field corrections. However, non-linear wafer deformations are usually strongest at the wafer edge. Therefore, specific high order field-by-field corrections are the ultimate correction method to mitigate the effects of these non-linear wafer deformations. However, determining the appropriate amount of high order field-to-field corrections is not trivial. At the wafer edge, exposure fields are often incomplete, so the fields contain less overlay marks and have a less regular distribution than fields that are completely on the wafer. Therefore, even on dense measurements, it is challenging to model these fields with a high order model without applying overcorrection. On the other hand, the metrology capacity for dense measurements is high, so these can typically only be performed with low frequency. Alternatively, smart field-by-field modeling algorithms are available to compute higher order effects based on reduced sampling plans. In this paper, we study different algorithmic approaches to optimize modeling algorithms for both dense and sparse (reduced) sampling plans. We compare the impact of varying the frequency of dense sampling to the performance of different modeling algorithms on sparse sampling.
© (2020) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Boris Habets, Stefan Buhl, Wan-Soo Kim, Patrick Lomtscher, Holger Bald, and Tobias Hoeer "Advanced high order field-to-field modeling for wafer edge control", Proc. SPIE 11327, Optical Microlithography XXXIII, 113270U (23 March 2020); https://doi.org/10.1117/12.2552714
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KEYWORDS
Semiconducting wafers

Data modeling

Performance modeling

Overlay metrology

Computer simulations

Data corrections

Metrology

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