In-situ electrical property quantification of memory devices by modulated electron microscopy

Muneyuki Fukuda; Kazuhisa Hasumi; Takashi Nobuhara; Hirohiko Kitsuki; Zhigang Wang; Kazuhiro Nojima; Yusaku Suzuki; Akira Hamaguchi; Masashi Kubo; Masaya Hosokawa

doi:10.1117/12.2658250

27 April 2023 In-situ electrical property quantification of memory devices by modulated electron microscopy

Muneyuki Fukuda, Kazuhisa Hasumi, Takashi Nobuhara, Hirohiko Kitsuki, Zhigang Wang, Kazuhiro Nojima, Yusaku Suzuki, Akira Hamaguchi, Masashi Kubo, Masaya Hosokawa

Author Affiliations +

Proceedings Volume 12496, Metrology, Inspection, and Process Control XXXVII; 124961O (2023) https://doi.org/10.1117/12.2658250
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States

Abstract

E-beam inspection based on voltage-contrast defect metrology has been widely utilized for failure mode analysis of memory devices. Variation in E-beam image contrast indicates shorts, opens and void defect inline inspection in the idle of production line. Meanwhile, accurate measurement of threshold voltage and the source-drain current is required to characterize memory cell through multi-layers. However, in the subthreshold region of memory cell, voltage contrast (VC) is weakened due to gate voltage stimulated by electron dose of e-beam scanning. We developed a modulated beam imaging with the SEM vector scan system to enhance VC contrast and defect inspection capability. Reliability of the modulated electron microscopy is validated by comparing with physical probing test result for process variation of Boron doping and annealing conditions in full wafer processing. VC with the modulated electron microscopy is well correlated to the probing test result. Image contrast of the modulated microscopy can differentiate contact via on floating circuit and disconnected floating circuit. We applied the modulated electron microscopy for in-line electrical defect detection at the middle of manufacturing line of integrated circuits. The defect distribution map by the modulated electron microscopy was confirmed to reproduce the physical probe test result. By achieving in-line electrical characterization before back end of line, yield loss issues can be detected and characterized two weeks earlier than conventional method. Moreover, this ability to detect and characterize memory cell issues inline is supposed to contribute to overcome the yield learning cycle bottleneck.

Conference Presentation

Citation Download Citation

Muneyuki Fukuda, Kazuhisa Hasumi, Takashi Nobuhara, Hirohiko Kitsuki, Zhigang Wang, Kazuhiro Nojima, Yusaku Suzuki, Akira Hamaguchi, Masashi Kubo, and Masaya Hosokawa "In-situ electrical property quantification of memory devices by modulated electron microscopy", Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 124961O (27 April 2023); https://doi.org/10.1117/12.2658250

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