This PDF file contains the front matter associated with SPIE Proceedings Volume 12954, including the Title Page, Copyright information, Table of Contents, and Conference Committee information.

In FinFET transistors, the parasitic capacitance between the source/drain contact and the metal gate tends to be high, and this can negatively impact device performance. Adding a metal gate recess step can reduce capacitance, but unfortunately it also increases the metal gate resistance. By changing the metal gate recess profile, a good balance between resistance and capacitance can be achieved to reduce RC. In this work, we investigate FinFET metal gate recess profile settings and how changes in profile settings affect FinFET resistance and parasitic capacitance (R and C). Metal gate recess dimensional changes and profile changes can modify parasitic capacitance and impact electrical performance. We performed a virtual DOE where we varied the gate CD, recess depths, and metal gate recess profiles to understand the impact of these changes on FinFET resistance, capacitance, and electrical performance. Different recess profiles, such as sharp head and antenna shapes, were simulated using SEMulator3D® virtual process fabrication and pattern dependence modeling. Subsequent electrical analysis was performed to extract resistance and capacitance values and to model device transistor behavior. We replicated the process to calculate the resistance and capacitance for a GAAFET, and investigated performance trends during changes in gate CD, tungsten (W) etchback and recess profile variations.

Stress technologies such as stress liners are used to improve the performance of advanced CMOS devices. Due to the contextual situation of a transistor in the physical design layout, unintended stress from neighboring cells can cause variations in the transistor characteristics. This effect is called Layout Dependent Effect (LDE). In this work we propose a fast method to detect outlier transistors due to the LDEs by profiling and sampling them from the VLSI design with millions of transistors and many devices. The proposed method can reduce the TAT for quantitative evaluation of the LDE for design layouts that have not passed the LVS. We also propose a pattern matching based method to search motifs created by encapsulating neighborhood of outlier transistors with large Vth variations. This enables designers to trace such LDE hotspot patterns and thereby outlier transistors during the design phase.

As semiconductor industry transitions to EUV lithography in advanced technology nodes, EUV stochastic defects play a significant role in chip yield degradation. Present yield models do not account for the stochastic-driven defects that changes by both pitches and critical dimensions (CD) in EUV lithography. In this study, a novel approach that incorporates EUV stochastics into the yield modeling, using calibrated stochastic defects from wafer data is introduced. Then a comparative analysis of yield for various EUV insertion scenarios is meticulously performed. Additionally, strategies to enhance yield in EUV lithography, including CD retargeting are proposed.

The integration of curvilinear shapes in semiconductor technology is explored. Curvilinear shapes are classified into forms using Manhattan, rectilinear, and curvilinear representations. The primary objectives of employing curvilinear shapes in Optical Proximity Correction (OPC) and mask technology are identified as error reduction and the effective representation of complex shapes. Leveraging the path optimization characteristic inherent in curvilinear shapes, their utilization was studied for semiconductor layout design. Standard cell design serves as a demonstrative example to highlight these benefits. Using the DTCO Power-Performance-Area-Cost (PPAC) assessment metric, enhancements in both electrical performance and cost efficiency are showcased, compared with designs using Manhattan shapes. We propose a step-by-step adoption strategy of curvilinear design, ranging from restrictive to partial use, and even free-form routing. In addition, we address concerns regarding data volume, outlining how curvilinear representation can effectively mitigate such issues, in OPC, mask technology and layout designs.

In the realm of Design for Manufacturability (DFM) optimization, Pattern-Based Layout Optimization (PBLO) has been a go-to approach for detecting and repairing DFM violations. However, to enhance the effectiveness of DFM rules in addressing hotspots, it becomes imperative to encompass a broader array of design situations (layout contexts). This expansion leads to an increased number of potential fixing guidance “hints”. Nonetheless, employing a static fixing hint order, unaware to the specific in-design topologies, can potentially diminish the output metrics i.e., fixing rate and runtime performance. In pursuit of optimizing these output metrics, we present an ML-powered PBLO workflow. In this innovative approach, a Machine Learning (ML) model is trained using an extensive dataset of preranked fixing guidance hints that are associated with a DFM rule. The topology aware supervised ML model is trained to dynamically guide and select the most suitable in-design fixing guidance order per situation, ultimately leading to an improved fixing rate, runtime and quality of results. In this study, we illustrate a workflow and mechanism for seamlessly integrating machine learning capabilities into the in-design fixing router. This involves developing multiclass machine learning algorithms and models to facilitate the generation of an optimal fixing guidance sequence.

DMCO combines both aspects of DFM (Design-for-manufacturing) with MFD (Manufacturing-for-design) and promises to accelerate overall design to manufacturing cycle time & overall chip PPAC by leveraging AI, Cloud scalability and big-data analytics to accelerate time-to-market for 2 nanometer and below.

The semiconductor industry is undergoing a major shift marked by the slowing of feature size reduction and the adoption of 3D processing techniques. The demand for increased computational power, driven by AI applications, has led to the proliferation of large die sizes. Achieving high yields in large, 3D-integrated designs presents new challenges. This presentation outlines a roadmap to address the unique obstacles associated with yield management for 3D processing. It highlights the point that failure patterns are not entirely random; certain layout styles have higher failure rates than others. Leveraging a collaborative, system-wide approach, it becomes possible to combine insights from various teams creating a group knowledge to pinpoint and fix systematic issues efficiently. A detailed system approach is proposed, with the identification of design sensitivities to electrical defects, grouping patterns into families for comparative analysis, utilizing end-of-line fault diagnostics to glean insights, and designing inspection experiments to determine failure rates.

Beyond FinFET device nodes, nanosheet is the next transistor architecture in CMOS scaling roadmaps. On top of the newer device architectures and materials, several other CMOS scaling boosters are being considered, and can help in further to improve the power, performance and area scaling. Backside power delivery network (BSPDN) is one of the promising scaling boosters, e.g. it disengages metal routing resources from the frontside, resulting in a lower routing congestion. Hence, the BSPDN booster paves the way for higher frequency and lower area footprint. However, ad-hoc standard cell design and optimization is required to connect the BSPDN network to the logic devices located in the front-end-of-line (FEOL). In this study, the implementation of different connection options to the BSPDN are studied in imec’s A14 nanosheet node: i.e. Through Silicon Via in the Middle of Line (TSVM), buried power rail (BPR) and direct backside contact (BSC). The different implications on standard cell design, as cell track height, routing and main process challenges are then compared to the classic frontside power delivery option. Finally, high-density (HD) standard cell libraries are implemented and characterized. Normalized area and delay comparisons at the library-level are presented. Area gains can rise up to 25% in case of BSC BSPDN option. Furthermore, maximum delay gains can vary up to 20% depending on standard cell type.

This article focuses on the application of Synopsys IC Validator (ICV) Pattern Matching in device extraction for customized devices in Integrated Circuit (IC) design. Customized devices play a critical role in achieving precision models. Having no additional or missing shapes in the region of customized devices is expected in order to keep the precision of models. To address this challenge, a robust methodology with an assistive debugging approach is required. Synopsys IC Validator Pattern Matching offers a solution that not only meets these requirements but also simplifies customized device representation and includes a user-friendly visualized debugger for efficient shape mismatch identification. The article provides a concise explanation of the device extraction flow with pattern matching (Figure 1), emphasizing the use of a pattern library containing source patterns. Pattern matching generates optional marker layers at matched locations by utilizing the pattern library in conjunction with the input design. In the context of Layout vs. Schematic (LVS) flow, the pattern library's source patterns consist of device layers like poly, active, and related layers, which form body and terminal layers. Pattern matching facilitates the extraction of body and terminal layers at matched devices, while any mismatch leads to missing device layers and their absence from the netlist. The effectiveness of IC Validator in delivering expected LVS results is demonstrated through the verification of live designs provided by customers, successfully identifying LVS fails for various design scenarios, including extra/missing/relocated polygons in the device region, extra connections to the outside of the device region, extra connections crossing the device region, pin swapping, and more. Additionally, the article presents a new pattern matching algorithm developed to optimize design turn-around times (TATs) for customized devices, such as inductors and capacitors. The algorithm leverages a multiplesteps pattern matching method, with a particular focus on efficiently filtering candidate target patterns. Through adjustments to the clipping-size in the first pattern matching step, a significant ~1.5x performance enhancement is achieved. In conclusion, the integration of pattern matching in device extraction proves to be a valuable approach, ensuring accurate IC design and validation by effectively handling customized devices. The enhanced pattern matching algorithm further optimizes design TATs, contributing to improved overall efficiency in IC design workflows.

Advanced technology nodes are beginning to adopt various technologies including innovations in transistor structure and MPT (Multi Patterning Technology) to achieve BEOL (Back End of Line) scaling. During DTCO (Design-Technology Co-Optimization) activity, BEOL geometries can be explored to achieve target PPA (Power-Performance-Area). To improve design's PPA, wire delay per unit distance can be reduced by increasing the metal width and spacing with given metal thickness. But increasing metal width and spacing can negatively affect the performance of the design as wire track resources per unit area reduced. Strengthening PDN (Power Delivery Network) can improve IR-drop of design, but also impact design's PPA negatively by consuming BEOL resource more. In this paper, application-driven metal stack and PDN optimization using ML (Machine-Learning) technique presented to address the issue effectively. To optimize metal stack and PDN, parameters of layer sheet count per thickness, pitch, spacing, and PDN horizontal/Vertical pitches are explored by Synopsys DSO.ai ML framework. DSO.ai optimization is constrained to maximize achieved frequency while maintaining certain IR-drop target. The metal stack and PDN optimization improved +2.2% of achieved frequency while 5.5% worse IR-drop. This is better frequency improvement than +1.4% of achieved frequency while 2.5% worse IR-drop from closest space where the DTCO done by human experts.

In modern digital integrated-circuit designs, standard-cell libraries are critical foundations. Transistor sizing can help determine an optimal set of transistor sizes of the standard-cell circuit under specified design constraints and desired circuit optimization goals. The conventional equation-based approaches can cause significant electric characteristic deviation, and the simulation-based approaches may be severely restricted by initial values. Recently, we proposed an improved transistor sizing method to compensate for the drawbacks. However, it did not consider the layout-dependent lithography effects. The printed wafer patterns can suffer from significant geometric distortions when layout geometry shrinks. It is worth investigating the lithography effects to ensure that the electrical characteristics of the manufactured devices can still meet the target design specifications. This work extends the effectiveness verification of the improved transistor sizing method by further considering the lithography effects. An in-house lithography simulation tool is utilized to generate wafer patterns. The electrical characteristics of transistors with non-rectangular gate shapes due to the lithography distortion are analyzed through different equivalent-gate-length estimation methods. The impacts of lithography effects on the optimized transistor sizes are characterized in several design cases.

We suggest advanced wafer engineering (i.e. Angle-ply Laminating Wafers(ALW)) which aim to tailoring and reducing wafer stress and distortion, in order to improve In-Cell Overlay(ICO) and On-Product Overlay(OPO). Especially, we focus ~nm devices adapting 3D-interconnection technology and scheme. In 3D-interconnection technology and scheme, Wafer to Wafer(W2W) bonding process are necessary harnessed. Unfortunately, it naturally induce large stress and distortion which are very sensitive to extrinsic and intrinsic property of wafer(i.e. initial warpage, thin film profile, wafer modulus). These wafer stress and distortion become a high risk in reducing overlay, as the cell size of device shrink. Thus, in development of ~nm devices, main key is to find effective and efficient method of wafer engineering reducing wafer stress and distortion. In order to handle this risk, we suggest and develop Angle-ply Laminating Wafers with heterogeneous crystal-structure, which is based on Classical Lamination Plate Theory(CLPT) in the area of advanced solid mechanics. By utilizing this design concept, anisotropic modulus of top and bottom wafer balance under W2W bonding process. As a result, it induce stress relaxation, distortion and reduce overlay. To verify it rigorously, we introduce the wafer stiffness tailoring method based on CLPT; and construct the simulation model predicting the W2W bonding distortion and photo overlay. We develop the W2W bonding simulation model based on framework of multiscale analysis and pre-verified by comparing with experiment results, which relate to the initial warpage effect on overlay and the thin film profile effect on bondability. Finally, we predict and analyze the effect of angle-ply laminating wafers with respect to a diverse combination of heterogeneous crystal-structure and stacking angle.

The concurrent saturation in dimensional scaling and increase in manufacturing cost and complexity has caused the overall semiconductor manufacturing cost to significantly increase. As a result, the cost per transistor is predicted to sharply increase in future technologies, deviating from the typical 30% cost per transistor reduction. This work explores the use of 3D-integration technologies, as wafer-to-wafer hybrid bonding, for both mobile and high-performance application. It is observed that the use of 3D-integration schemes, can reduce the overall die cost at same functionality, paving the way for cost-effective scaling solutions in future technologies.

With advanced semiconductor technologies continuing to evolve, defect prediction has experienced increased challenges because process issues involve complex interactions of multiple-layer layout patterns. This makes it more challenging than before for traditional pattern search techniques to identify, predict, and fix the process issues in a short time. Also, due to the increased cycle time to introduce new semiconductor technologies, for Integrated Circuit (IC) design houses with early technology engagements, finding potential defects in these new technologies and improving design quality become more challenging than before. Oftentimes utilization of previous learning experience for detecting and reducing defects becomes unavoidable. To overcome these difficulties, a feature-based artificial intelligence/machine learning (AI/ML) defect prediction tool has been developed and utilized to improve the prediction of potential process defects for IC designs. With this tool and its workflow, with the previous technology process improvement learning experience, the defect patterns are generated to improve design qualities for the new technology. The tool also provides functions of clustering and compressing the predicted defect patterns that facilitate finding root causes of the process defects. This paper will describe the new defect prediction flow, especially using previous technology process improvement data to analyze similar issues in the current technology designs.

Post-exposure bake (PEB) consists of neutralization, diffusion, and catalysis steps, and are modeled by partial differential equations (PDEs). Commercial PEB simulation relies on numerical methods to explicitly solve PDEs in both spatial and temporal domains, and is very time consuming. A machine learning model has been applied to quickly predict the final inhibitor distribution with initial acid distribution as a model input. The accuracy, however, is not good enough; for different PEB condition comprising baking time and temperature, the model should be trained again, which is another limitation. A recurrent neural network (RNN) is proposed for fast PEB simulation. The network is constructed around convolutional long short-term memory (convLSTM), which is a popular RNN for spatio-temporal prediction. Key inputs of convLSTM include the encoded values of acid and quencher distributions as well as their multiplication; acid and quencher distributions on next time step are obtained after the outputs of convLSTM pass through decoders. Once acid distribution is derived at time instance of interest, inhibitor distribution is extracted directly from its PDE. To accelerate RNN prediction, operations are skipped and the distribution at the next time step is simply copied from the one at the current time step if PEB reaction does not occur. Experiments have shown that the runtime of PEB simulation is reduced by 88.1% with smaller total PDE loss by 35.3%, compared to commercial tool.

For advanced technology nodes, it’s critical to utilize resolution enhancement technique (RET) methods to improve pattern fidelity and wafer yield. Conventional techniques including rule-based SRAF (RB-SRAF) and model-based SRAF (MBSRAF) methods have been widely adopted to increase the manufacturing process window. ILT delivers superior imaging performance compared to both RB-SRAF and MB-SRAF methods, at the expense of slower performance and more inconsistency issue. Recent advancement of machine learning techniques opens up new gateways for more RET enhancements by overcoming these challenges, thus providing a pathway to extend ILT solution to full chip design. In this paper, we developed an end-to-end flow that seamlessly incorporated model training and application for full chip ILT MBSRAF generation and optimization via POLY-GAN, a new Generative Adversarial network (GAN) geared for fast, in-context and accurate ILT MB-SRAF synthesis. An image based deep learning architecture similar to pix2pix conditional GAN was utilized in our study. In this paper, we demonstrate that ML based full chip ILT MBSRAF generation yields superior process window compared to rule based SRAF generation, while maintaining comparable run-time performance.

Mask 3D (M3D) effects distort diffraction amplitudes from EUV masks. Electromagnetic (EM) simulations are used to rigorously calculate the distorted diffraction amplitudes. However, EM simulations are highly time consuming for OPC applications. The distorted diffraction amplitude can be characterized by M3D parameters. We develop a convolutional neural network (CNN) model which predicts M3D parameters very fast from input mask patterns. In this work, we train CNN using test mask data with various characteristics of metal layers. The accuracy of the CNN is good for the test mask data. However, when we use new mask data that mimic device patterns, the accuracy of the CNN is worsened. Starting from the CNN pre-trained by the test mask data, we improve the accuracy of the CNN by additional training using larger dataset including both the test mask data and the new mask data. The accuracy of the CNN is slightly improved by the fine tuning.

The rapid evolution of the electronics industry, driven by Moore’s law and the proliferation of integrated circuits, has led to significant advancements in modern society, including the Internet, wireless communication, and artificial intelligence (AI). Central to this progress is optical lithography, a critical technology in semiconductor manufacturing that accounts for approximately 30% to 40% of production costs. As semiconductor nodes shrink and transistor numbers increase, optical lithography becomes increasingly vital in current integrated circuit (IC) fabrication technology. This paper introduces an open-source differentiable lithography imaging framework that leverages the principles of differentiable programming and the computational power of GPUs to enhance the precision of lithography modeling and simplify the optimization of resolution enhancement techniques (RETs). The framework models the core components of lithography as differentiable segments, allowing for the implementation of standard scalar imaging models, including the Abbe and Hopkins models, as well as their approximation models. The paper introduces a computational lithography framework that optimizes semiconductor manufacturing processes using advanced computational techniques and differentiable programming. It compares imaging models and provides tools for enhancing resolution, demonstrating improved semiconductor patterning performance. The open-sourced framework represents a significant advancement in lithography technology, facilitating collaboration in the field. The source code is available at https://github.com/TorchOPC/TorchLitho.

Contour-based OPC modeling has recently arisen as an alternative to the conventional CD-based method. In this work, an innovative flow is proposed to improve the quality of the final calibrated model by using SEM image contours. Layout pattern sampling technique should be introduced into this flow, which could not only ensure adequate coverage including IPS and pattern diversity, but also minimize the data collection effort. In this study, we have developed an automated high-precision contour extraction method to obtain good and reliable contours that were in good agreement with traditional CD-SEM measurements. The OPC model calibration was built by using the high-precision SEM contours, and we compared the contour-based method with conventional CD measurements. Finally, the model error RMS of the calibration and verification process could be fed back to the layout pattern sampling, which could benefit the sustainable improvement of the predictive ability of the model.

Extreme ultraviolet lithography (EUVL) with a NA of 0.33 has been part of high-volume manufacturing since 2019. To guarantee the downscaling of the technology node, advanced material and patterning becomes very critical in terms of resolution, roughness, defectivity and process window. Therefore, several entities are developing new resists and processes. However, to adopt new resist and process into the production, performing model based optical proximity correct (OPC) is an essential step. Thus, an accurate OPC model is required. In this paper, we investigate the calibre CM1 OPC model accuracy of dry resist process, which is conducted on N5 M2 design (pitch 32nm).

In this work we introduce an Inverse Lithography Mask Design (ILMD) framework for Displacement Talbot Lithography (DTL), an emerging photolithography technique utilized especially for various photonic applications. Image formation process in DTL differs from projection or proximity lithography techniques. In DTL, the printed pattern is generally not an “image” of the mask in any common sense of the word, as there exists a rather complex relationship between the mask and wafer patterns. This has prevented the use of DTL for printing patterns other than simple shapes such as circles or squares up to now, as there are no obvious solutions to even start from, like those that exist for projection or proximity methods. Our ILMD framework, powered by an optimization method overcomes this hurdle. It takes a targeted wafer pattern as the input and yields potential mask geometries as the output. To verify the efficacy of the ILMD framework, we designed DTL masks for a variety of complex geometries. We realized a number of the resulting mask layouts using standard fabrication methods and used them in DTL exposures to print the intended patterns. The validity and accuracy of the ILMD framework was confirmed by SEM imaging of the printed patterns. This work proves the general capability of DTL’s underlying optical principles to produce complex periodic patterns. It significantly broadens the application scope of the DTL technique by providing a practical and efficient design route.

One of the key methods targeted for continuing the resolution scaling in new device technology nodes is the trend towards using curvilinear mask patterns. With recent advances in multi-beam mask patterning and large-scale adoption of ILT mask data correction, curvilinear (and all-angle) mask patterns are considered today as a mainstream technology option. Curvilinear mask patterns provide improved wafer resolution and OPC/ILT mask correction control with reduced mask manufacturing issues related to tight corners and line-ends. However, OPC, ILT, LRC and other full-chip simulation-based mask synthesis methods also require more accurate electromagnetic (i.e., M3D) simulation for new technology nodes. Prior full-chip electromagnetic simulation methods have often assumed that mask patterns are restricted to Manhattan geometries or utilize limited angles. Therefore, there is a general industry need for improved electromagnetic full-chip simulation methods for curvilinear mask patterns. This paper will present a new electromagnetic full-chip simulation method for curvilinear mask patterns that will improve the accuracy of mask synthesis methods at upcoming technology nodes. This method can provide both accuracy and speed benefits on mask synthesis with curvilinear mask patterns for both DUV and EUV lithography. The method utilizes an enhanced physics-based treatment of electromagnetic mask scattering both tuned and verified by rigorous electromagnetic Maxwell’s equation solvers.

Advanced computational lithography requires growing compute power and increased flexibility which can be easily accessed on Cloud. We’ll present solutions developed to allow Calibre semiconductor manufacturing PTOF jobs to leverage Cloud massive compute power seamlessly and cost-effectively. An OPC–MPC–MDP PTOF flow launched under Siemens EDA Reference Environment for AWS will demonstrate the following optimizations: keep Cloud instances busy and provide best runtime by dynamically scaling the jobs and the cluster size; use AWS spot instances seamlessly; monitor jobs and hardware at the same time to fine-tune cloud instance types; reach massive scalability using Calibre FullScale.

Driving the silicon photonics technology along the journey of early development towards high volume manufacturing passes through multiple challenging stages. In this presentation I will be focusing on the challenges facing both optical proximity correction (OPC) and etch compensation for silicon photonics designs versus conventional CMOS designs.

As layout schemes become increasingly complex for advanced technology nodes, challenges such as large edge placement error (EPE) and poor OPC convergence in optical proximity correction (OPC) can lead to significant yield losses. To overcome these issues, widely adopted strategies include layout re-targeting before OPC and mask feature modification after OPC for mask synthesis. The former entails adjusting the after-development inspection critical dimension (ADI CD) target of the original design layout. However, this process often relies on a time-consuming trial-and-error iterative approach to determine optimal sizing values for specific layouts. In recent years, machine learning techniques have shown promise in computational lithography, offering efficiency improvements. Leveraging the advantages of machine learning for guidance on layout re-targeting has the potential to reduce turnaround time. This paper presents a methodology that incorporates deep generative models into the layout re-targeting flow to propose proper sizing values for the layout of 3D NAND channel holes. Initially, we train two different deep generative models, namely Generative Adversarial Networks (GANs) and the Diffusion Model. These models are employed to infer sizing values for pre-OPC patterns through model prediction, utilizing input error data. Subsequently, the inferred sizing values are input into the design rule check (DRC) commands for polygon movement. Experimental results demonstrate that both deep generative models can predict layout sizing in the re-targeting flow, resulting in significantly improved accuracy of ADI CD and reduced turnaround time compared to the traditional trial-and-error approach.

As Moore’s Law continues to increase the complexity of electronic systems, Electronic Design Automation (EDA) must advance to meet global demand. An important example of an EDA technology is SKILL, a scripting language used to customize and extend EDA software. Recently, code generation models using the transformer architecture have achieved impressive results in academic settings and have even been used in commercial developer tools to improve developer productivity. To the best of our knowledge, this study is the first to apply transformers to SKILL code autocompletion towards improving the productivity of hardware design engineers. In this study, a novel, data-efficient methodology for generating SKILL code is proposed and experimentally validated. More specifically, we propose a novel methodology for (i) creating a high-quality SKILL dataset with both unlabeled and labeled data, (ii) a training strategy where T5 models pre-trained on general programming language code are fine-tuned on our custom SKILL dataset using self-supervised and supervised learning, and (iii) evaluating synthesized SKILL code. We show that models trained using the proposed methodology outperform baselines in terms of human-judgment score and BLEU score. A major challenge faced was the extremely small amount of available SKILL code data that can be used to train a transformer model to generate SKILL code. Despite our validated improvements, the extremely small dataset available to us was still not enough to train a model that can reliably autocomplete SKILL code. We discuss this and other limitations as well as future work that could address these limitations.

The need for resolution scaling in new device technology nodes is a long-standing trend in semiconductor patterning. As DUV lithography will not go beyond the current 1.35NA and high-NA EUV lithography has not yet been introduced intro production, fabs are pushing to achieve higher resolution in upcoming device nodes by lowering the lithographic k1. DUV lithography is being pushed well below the 80nm minimum pitch value and EUV lithography is also being pushed to continue shrinking beyond current pitch limits. Lower k1 lithography causes increased sensitivity to process variations but tighter EPE control is required in new nodes. Consequently, new methods for improving EPE control and reducing lithographic errors and hotspots are needed well beyond current 2D compact resist modeling applications. This paper discusses new improvements in EPE control and hotspot reduction by improving the accuracy of full-chip three-dimensional (3D)-aware resist compact modeling. These improvements are enabled by better integration and learning for compact models with rigorous 3D resist models that take advantage of enhancements in traditional and machine-learning modeling as well as data handling.

Extreme ultraviolet (EUV) technology enables further downscaling for logic and memory designs. This powerful technology comes with new challenges that must be controlled to unlock the novel technology accuracy and capabilities. Freeform (curvilinear) masks introduce a flexible tape-out capability that enables customers to realize EUV technology accuracy and capabilities on wafer. However, the accuracy enhancements of curvilinear masks do not come free of challenges. Source optimization, optical proximity correction (OPC) and verification runtime, mask proximity correction (MPC) runtime, data volume handling at fracture, and finally mask writing time are some of these challenges. In this paper, we present an affordable runtime tape-out flow for optical proximity correction and verification. This tapeout flow connects the capabilities of different engines to balance accuracy and mask turnaround time. Combining the benefits of rigorous solvers and pattern matching with affordable OPC, mask rule check (MRC) and verification capabilities cut down mask turnaround time from weeks to days, offering customers cutting edge technology on wafers with acceptable runtime. In this paper, we present a new flow for EUV freeform OPC with demonstrated runtime and accuracy benefits validated on wafer

In this paper we will evaluate the impact of stitching on process window and show how EDA can help to improve the manufacturability of stitched layers. More specifically, we demonstrate modeling of double exposure effects suitable for full-field correction and verification that incorporates aerial image cross-talk, optical black border transitions, subresolution gratings, sub-resolution assist-features and long-range flare. We also evaluate how stitching impacts different high NA processes and how correction of these effects (ex. via optical proximity correction, inverse lithography technology) can be used to increase process robustness. Finally, we examine the impact of stitched pattern overlap to process window and how loss of process window due to stitching can be mitigated.

In this paper, we present a rigorous simulation engine for DSA chemo-epitaxy patterning processes. The model can be utilized to predict the post-process patterns for line space and hexagonal hole layouts. Traditional pitch-split and EUV pattern rectification process integration schemes are simulated. The model output for Line Edge Roughness (LER) and Pattern Placement Error (PPE) is compared to the experimental results. Finally, we will explore how to enable DSA-aware process-compliant designs, taking into account cut-mask considerations in the context of design rules.

High numerical aperture (NA) extreme ultraviolet (EUV) lithography single patterning is evaluated through source mask optimization (SMO). The patterning performance is assessed on random logic metal design with minimum pitches of 24, 22, and 20nm in the horizontal direction to confirm the feasibility of logic metal scaling. We set a 1 square micron as a cell window and choose 200 gauges to include various types of features such as dense, isolated, and tip-to-tip. SMO is performed assuming eight permutations of a) dark-field versus bright-field, b) Ta-based versus low-n attenuated phaseshift masks, and c) with sub-resolution assist feature (SRAF) versus without SRAF. For each design, the process window is estimated.

Grayscale lithography (GL) is a well-suited technique to manufacture 3D micro objects, such as micro-lens, in a single lithography step. The current method to realize GL masks is limited to square pattern masks and suffers from a high computational cost. This article introduces a deep learning workflow to generate free-form masks for GL. The proposed workflow is composed of five main steps: the dataset generation, the neural network training and inference, the post-treatment and its evaluation. With this method, quality index for 3D simulated objects is equivalent to the current iterative computational method and the computation time is reduced at the same time.

Computational technologies are still in the course of development for nanoimprint lithography (NIL). Only a few simulators are applicable to the nanoimprint process, and these simulators are desired by device manufacturers as part of their daily toolbox. The most challenging issue in NIL process simulation is the scale difference of each component of the system. The template pattern depth and the residual resist film thickness are generally of the order of a few tens of nanometers, while the process needs to work over the entire shot size, which is typically of the order of 10 mm square. This amounts to a scale difference of the order of 106 . Therefore, in order to calculate the nanoimprint process with conventional fluid structure interaction (FSI) simulators, an enormous number of meshes is required, which results in computation times that are unacceptable. To support all lithographic systems, Canon has introduced “Lithography Plus”, a software solution capable of anomaly detection, automatic recovery, trouble flow prediction and remote support. The software is now under development specifically for NIL. Because NIL is a rheological process, to software must address a completely new work flow. In this paper, we introduce the methods used to create drop patterns and refinements to the NIL process simulator which can be applied to predict resist filling and, in the future, be used to make corrections to the drop pattern virtually, thereby eliminating time consuming on-tool verification. Finally, we discuss the development of virtual metrology software that incorporates artificial intelligence to provide fast feedback on key tool outputs such as overlay.

A pattern replacement in-design auto-fixing methodology, called MAS-POP, is developed to increase the scores calculated by the Manufacturability Analysis and Scoring (MAS) tool, improving the compliance with DFM rules. A library of patterns is developed using pattern classification automation, converting multiple types of Back-End-Of-Line (BEOL) DFM rules to patterns: via-metal line end enclosure, metal 2 tip-to-tip spacing, and metal area. Corresponding fixing hints are prescribed for each pattern. Once the library of patterns and the associated fixing hints have been developed, they are integrated with the router to utilize its pattern replacement feature. This insertion identifies matching patterns and fixes the violations by applying the prescribed fixing hints, improving the usage of the DFM rules and enhancing the MAS scores. The MAS-POP methodology is demonstrated on routed designs. Results show that for a 200 x 200 um2 block, three via-metal line end enclosure patterns reduce the number of DFM violations from 12.5k to 360 on one 2x metal layer, with a small runtime impact.

The yield of the deep sub-micron semiconductor is secured by the process capability as well as the yield-friendly design capability. Yield-friendly design capabilities can be equipped with conventional Design for Manufacturability (DFM) that avoids already known defective layouts in design. Previously known defects can be defined as various rules and avoided in design, but defects that may occur at new technology nodes are difficult to avoid in advance. Indiscreetly defect-avoidance designs cause turn TAT increases and Power/Performance/Area (PPA) overheads in the design, which can ultimately lead to increased design costs and poor design competitiveness. The first step of this study is to predict potential risks and to specify major factor of risks that may occur at new process nodes with new DFM solutions developed using Machine Learning (ML) techniques. The second step is to secure early yield through avoidance design to prevent predicted defects and direct mask modification to improve defects. In this study, we present not only the introduction of new ML-based DFM solutions, but also the effect of predicting and improving defects through the application cases of real products.

A digital twin is a numerical copy of an asset or a process, used to predict its physical behavior over time. Usually, a digital twin is based on physical models, constructed by simulating its different parts. It is then used to monitor and act on systems, based on digital state information, which is computed from real sensors data that feed the digital twin. Among the usages, we can cite predictive maintenance, planification, root cause analysis among others. We propose to adapt the technology to monitor and model complex processes by data driven, it can also be used in complement of physical simulation. Our proposal is a framework to create Artificial Intelligence (AI) models based on experimental data, then simulate new recipes and optimize the process, including constraints defined by the Process Engineer. AI models can be enriched with physical models; when available, they are used to create additional training data and to compare AI models with simulation. AI models require clean data, this procedure is tedious and time consuming. Depending on the process, it can be simplified by proposing automatic processes to clean and arrange data so that it can be used directly for training. The use of AI in comparison to classical physical models allows users to identify bias in their selection of parameters. It is used as a proxy for accurate optimization of the process under constraints. It can also serve to explore more efficiently the parameters space, by avoiding experiments that would lead to low performances. Finally, several tools are proposed to improve the understanding of the complete process and visualize the relationships between parameters and characteristics of the product. We propose an experimental setup using physical simulations of semiconductor materials to demonstrate the use of our digital twin pipeline.

In prior work, as a means to overcome computational cost while maintaining similar ILT lithographic quality, we presented full-chip layout synthesis with curve-based OPC as a complimentary option with curvilinear ILT. However, there are an increasing number of different quality determinations, cost constraints and orthogonal solutions needed for curvilinear mask and target correction to meet the requirements for different layers (L/S, CH/Via/Cut-mask), devices (logic, DRAM, Flash) and lithographic applications (DUV, EUV, photonics, flat-panel display, High NA EUV), etc. In this paper, we will share a spectrum of advances for curvilinear masks and targets by ILT, and integrated curve-based ILT/OPC. These varied solutions can achieve the quality and computational cost requirements for the different application areas previously listed. Additionally, we will also describe new advancements in adjacent areas of the curvilinear mask ecosystem for MRC, MEC, etch and data volume reduction.

Low-cost and high-precision fabrication of surface relief gratings on AR/VR waveguide combiners is one of the critical steps in realizing devices suitable for mass adoption. Displacement Talbot Lithography (DTL) has emerged as a viable technology that relies on the proven optical lithography approach of the semiconductor industry while offering a low-cost solution for large area printing of periodic structures of the kind required on waveguides. However, patterning with DTL differs from the common projection photolithography approaches in terms of the optical concepts used in printing an image in a photoresist layer. A key capability required for mass adoption is accurate simulation support for faster integration, process optimization, and mask design. Electronic Design Automation (EDA) tools are common for projection approaches and can now be used to understand DTL interactions with waveguide designs. This approach relies on three specific Synopsys modeling tools, namely S-Litho and RSoft Photonic Device Tools in conjunction with LightTools which are used for optimization of the photolithographic printing process (DTL) and the optical performance of the printed device (waveguide), respectively. A dedicated suite for modelling the DTL process within the S-Litho software was developed for this purpose. The model is calibrated and optimized using actual printing results in photoresist layers obtained through the DTL process. In this presentation we will show results of this new method that combines the optimization of DTL lithographic printing and optical performance of the resulting waveguide. The combination of the unique DTL solution and the comprehensive simulation capabilities holds great promise for accelerating the development and commercialization of AR devices.

Curvilinear(CL) mask shapes have showed better lithography performance, including improved process window, better PVband and MEEF compared to Manhattan mask. With the development of Multi-Beam-Mask-Writer (MBMW), the adoption of CL mask in production becomes reality. However, there are multiple challenges associated with CL data, such as complex mask shape and large data volume. One of the most important challenges is to have a good set of Mask-Rule-Check(MRC) rules which is essential to achieve good OPC mask quality. Calibre® OPCVerify has been developed for years to check CL shapes. Combining with existing checks, a full suite of CL MRC checks has been added. In this paper, we will present a fully integrated CL verification flow.

The photomask industry is experiencing a fundamental shift from Manhattan masks to curvilinear masks. In the recent lithography and mask technology conferences, there were many papers and talks on curvilinear masks, curvilinear OPC, curvilinear ILT, curvilinear mask process correction (MPC), and curvilinear mask formats. Step by step, the photomask industry has started a transition from Manhattan to curvilinear, enabled by the adoption of the new multi-beam mask writers and the advent of practical full-chip curvilinear inverse lithography technology (ILT). The benefits of curvilinear masks go much deeper than is immediately obvious. In this paper we will share our insight on why the mask world is moving toward curvilinear mask shapes. We will demonstrate that curvilinear masks are more reliably manufacturable. We will evaluate the benefits of curvilinear in terms of process window, mask rules, mask error enhancement factor (MEEF), and mask variation.

Inverse lithography technology (ILT) and Curvilinear masks (CL masks) are playing a critical role in addressing the challenges of EUV as we move toward advanced nodes. However, CL masks may have shapes that are more challenging to Mask Rule Check (MRC) clean-up and mask manufacturing, like sharp angles, T/Y junctions, sharp turns, and too-small features. Running a CLMRC checks before mask making is a general practice that allows to quickly screen the full chip and identify potential mask problems before mask inspection. Last year, we presented one of the CLILT solutions to address the MRC challenges on the CLILT masks [1,2 and 3]. In this paper, we present a comprehensive study of the curvilinear Mask Rule Check (CL MRC) quality and runtime. We compare and discuss different CL MRC check and quality of the results. We will describe how to properly filter measurements to flag true MRC violations while excluding false violations. Finally, we demonstrate a flow to achieve significant runtime improvement on a full chip database.

Siemens EDA (Mentor) has published their pioneering work on matrix OPC at SPIE before, in the same title but part I and II. Based on this work, an OPC feature MatrixOPC has been developed at Siemens EDA (Mentor). The MatrixOPC feature is now used by customers in production recipes routinely. However, this work was only focused on rectilinear OPC or Manhattan masks. In this paper, we present our current effort in generalizing the rectilinear matrix OPC to the curvilinear mask setting and to curvilinear OPC. Our initial test with a particular test case shows a promise that the new version, curvilinear matrix OPC and still under development, may also become a useful supplemental instrument for our curvilinear OPC solutions, compared to the curvilinear OPC practices without it. In this paper we will define the Jacobian matrix for the curvilinear mask setting, and compare the Jacobian matrices obtained from the brute-force definition and from our fast approximation algorithm, by comparing their total differentials. We also compare the OPC results from regular curvilinear OPC and matrix OPC with a fast approximated Jacobian.

The calibration of optical proximity correction (OPC) models has become increasingly challenging, especially when the behavior of photoresist on wafers cannot be adequately interpreted using conventional model terms assembled in a linear fashion. Additionally, fine-tuning such linearly separable physical components proves difficult due to evidence of nonlinear interactions among physical effects. In this study, we propose leveraging an advanced regression technique that progressively augments the linear model assembly with perturbative nonlinear neural network units the sharing same set of physics-inspired model terms as its base model, aiming to enhance model accuracy while maintaining stability. The research approach involves setting up initial models using conventional model calibration techniques, including optical model optimization and resist model optimization. Subsequently, we incorporate the Synopsys Advanced Regression (AR) neural network to identify essential non-linear interactions among modeling components. We selectively include these non-linear components into the existing linear model to capture on-wafer behavior. The entire process is designed to integrate seamlessly into the existing OPC production flow, ensuring a balance between model accuracy and efficiency. To evaluate the efficacy of the Synopsys AR method, we conduct tests on layers from 3D-NAND. The results demonstrate that this approach significantly reduces calibration costs due to its simpler calibration requirements.

In EUVL, aberrations play a crucial role in critical dimension (CD) and pattern shift (PS) errors. It is significant to decide aberration compensation and optimization strategies for compensating exposure errors. The modeling process of aberration is time-consuming, mainly because of the need to consider numerous aberrations. In order to save the runtime for aberration modeling, this paper proposes a methodology for identifying the key aberrations that have significant impacts on imaging results. Three different techniques are employed and compared, including single parameter sensitivity analysis, definitive screening design (DSD) method, and SOBOL method that consider the coupling effects of different orders. By comparing the deviations between the imaging results considering only key aberrations and all aberrations, it is found that the identified aberrations achieve extremely high accuracy for various patterns and illumination conditions. Even though the proportion of key aberrations among all aberrations is only a small fraction. All the three methods can achieve that the average CD and PS deviations do not surpass 1%, using 40% of the total 37 aberration items. Thereby, the feasibility of using identified key aberrations for aberration modeling is validated. In addition, we also compare the accuracies of three techniques under the same conditions and found that the SOBOL method is the most suitable technique for identifying key aberrations. Consequently, for specific illumination conditions and corresponding layout patterns, the use of key aberrations is an effective way to characterize the impacts of all 37 aberrations, accelerating the aberration compensation and optimization without sacrificing accuracy.

Process Window Qualification (PWQ) is a well-known wafer inspection technique used to qualify the IC manufacturing lithography process window. Circuit designs are becoming denser and more complex in advanced semiconductor process technologies. Therefore, yield is becoming increasingly sensitive to defects. How to detect wafer defects at an early stage is the key to improving wafer yield. Additionally, shortening the PWQ total turn around run time is an important factor for a wafer yield improvement methodology. In this paper, the Winbond OPC team and Cadence Pegasus DFM team initiated a project to improve the PWQ run time and accuracy using a pattern analysis flow. This flow includes defect data pre-processing, classification, and filtering, including the use of CD-SEM image auto-alignment to improve extraction locations and wafer results. The huge data volumes are reduced in order to create easy to review results. This flow reduces the PWQ processing time and correctly finds real wafer defects to improve process windows and yield.

Test pattern selection plays a vital role in the model calibration in the optical proximity correction process. Traditional OPC resist models mainly use the image parameters such as the minimum intensity, the maximum intensity, the slope of intensity along the cut lines crossing the gauge points as their input parameters to calculate the resist contour position. To guarantee the accuracy of the resist model over the whole design layout, it is important that the image parameter space of the test patterns used to calibrate the OPC model covers the image parameter space of the original design layout. We present a method to generate test patterns based on the provided image parameters. The method is based on the adversarial neural network. With this method, we can prepare the test patterns with the desired image parameter coverage.

In this paper, we systematically explore potential Line edge roughness (LER) improvements that may be achieved on both line and via patterns by using the deposition/etch cycling process by virtual fabrication. The results show that deposition/etch cycling process is very effective in reducing high frequency noise and most of the LER and CD uniformity improvement occurs during the first deposition/etch cycle. These results can provide quantitative guidance on the optimal selection of deposition/etch amounts and the number of cycles needed to reduce LER.

This study delves into the convergence challenges of Inverse Lithography Technology (ILT) in advancing Optical Proximity Correction (OPC). While ILT shows promise, it faces runtime hurdles and intricate stitching issues caused by data inconsistencies at tile boundaries, particularly in complex corrections. Here, we perform a comprehensive and comparative analysis of the run time and data consistency at tile boundaries for four gradient descent-based algorithms: Steepest Descent (SD), Momentum, Adaptive gradient, and Adaptive Moment Estimation (Adam). Our findings reveal that stitching problems arise from insufficient ambient range and convergence issues during ILT optimization. We recommend using an ambient size equal to or larger than the kernel size. Furthermore, we show that robust convergence can mitigate data inconsistency challenges, even with a limited ambient range. Notably, Adam emerges as a powerful solution, offering substantial runtime acceleration, often ten to hundreds of times faster than SD. Renowned for its prowess in optimizing complex models and GPU-accelerated parallel processing, Adam is a key strategy for expediting computational lithography in semiconductor manufacturing, paving the way for future advancements in ILT.

Etching process is an indispensable patterning step in semiconductor device manufacturing. The etch bias compensation is critical in optical proximity correction (OPC) to ensure lithography fidelity and device performance. Therefore, accurate prediction of etch bias has become more crucial as moving to advanced technology node etching process. This study aims to develop an etch bias prediction model based on ensemble learning, specifically utilizing the Random Forest algorithm. A substantial simulation results comprising linewidth, pitch, and corresponding etch bias data for one-dimensional layouts was collected. Subsequently, we employed the Random Forest algorithm, a powerful ensemble learning method, to construct the etch bias prediction model. Random Forest effectively captures the intricate relationships between linewidth, pitch, and etch bias by combining multiple decision trees. Finally, we utilized transfer learning techniques to fine-tune a pre-trained random forest model using real experimental data, resulting in the final model. Compared to traditional machine learning methods, such as the BP neural network, this approach features with faster training speed and better robustness, the Random Forest model exhibits stronger transferability across different technology nodes and different process conditions.

Bitline contact (BLC), bitline (BL), and node contact (NC) fabrication are three interacting process loops during DRAM fabrication. BLC characteristics play an important role in subsequent BL and NC process loops. The complex structure of DRAM increases the difficulty of identifying the impact of BLC process variations on device shorts (BVC test failures) and device opens (DVC test failures). In this work, virtual DOEs using SEMulator3D® (Lam Research’s virtual fabrication platform) were carried out to better understand the effect of BLC characteristics on DVC and BVC failures, including BLC X and Y axis CD, etch sidewall angles, overlay (OVL) shift and roughness. From our studies, we have developed optimized process specification for X and Y axis CD, etch sidewall angles, OVL shift, and roughness during the bitline contact process loop. The results of this type of experiment can help developers identify key specifications and save resources during the early design phase of DRAM process development.

A prevalent practice in semiconductor fabrication involves the utilization of Graphic Data Systems (GDS) for sampling within the Fab. However, with the reduction in process nodes, the capacity and intricacy of GDS escalate, making efficient and accurate sampling increasingly imperative. The emphasis on sampling varies across diverse application scenarios within the factory. This article delves into the application of machine learning methods to enhance sampling efficiency for Fab applications. It encompasses a spectrum of applications, notably the Photo Resist change project, where machine learning-based sampling techniques are deployed to streamline inspection points. Additionally, the article investigates the potential of machine learning in mask Critical Dimension (CD) performance verification, facilitating real-time monitoring of mask performance through optimized sampling strategies. Moreover, the implementation of SEM down sampling in the defect review process, driven by machine learning, demonstrates the capacity to boost defect hit rates and proficiently identify missing real defects.