Advances in full-chip three-dimensional resist modeling for low k1 EUV and DUV lithography

Elizabeth Grubbs; Bernd Kuechler; Hyesook Hong; Enas Sakr; Lena Zavyalova; Folarin Latinwo; Delian Yang; Linghui Wu; Yan Feng; Kevin Lucas

doi:10.1117/12.3013125

10 April 2024 Advances in full-chip three-dimensional resist modeling for low k1 EUV and DUV lithography

Elizabeth Grubbs, Bernd Kuechler, Hyesook Hong, Enas Sakr, Lena Zavyalova, Folarin Latinwo, Delian Yang, Linghui Wu, Yan Feng, Kevin Lucas

Author Affiliations +

Proceedings Volume 12954, DTCO and Computational Patterning III; 129540S (2024) https://doi.org/10.1117/12.3013125
Event: SPIE Advanced Lithography + Patterning, 2024, San Jose, California, United States

Abstract

The need for resolution scaling in new device technology nodes is a long-standing trend in semiconductor patterning. As DUV lithography will not go beyond the current 1.35NA and high-NA EUV lithography has not yet been introduced intro production, fabs are pushing to achieve higher resolution in upcoming device nodes by lowering the lithographic k1. DUV lithography is being pushed well below the 80nm minimum pitch value and EUV lithography is also being pushed to continue shrinking beyond current pitch limits. Lower k1 lithography causes increased sensitivity to process variations but tighter EPE control is required in new nodes. Consequently, new methods for improving EPE control and reducing lithographic errors and hotspots are needed well beyond current 2D compact resist modeling applications. This paper discusses new improvements in EPE control and hotspot reduction by improving the accuracy of full-chip three-dimensional (3D)-aware resist compact modeling. These improvements are enabled by better integration and learning for compact models with rigorous 3D resist models that take advantage of enhancements in traditional and machine-learning modeling as well as data handling.

Conference Presentation

Citation Download Citation

Elizabeth Grubbs, Bernd Kuechler, Hyesook Hong, Enas Sakr, Lena Zavyalova, Folarin Latinwo, Delian Yang, Linghui Wu, Yan Feng, and Kevin Lucas "Advances in full-chip three-dimensional resist modeling for low k1 EUV and DUV lithography", Proc. SPIE 12954, DTCO and Computational Patterning III, 129540S (10 April 2024); https://doi.org/10.1117/12.3013125

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available