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Advanced packaging enables the heterogeneous integration of different components, to integrate functional devices needed for the ever-diversifying needs of compute market. For advanced packaging to achieve a high level of integration, the package substrate must be densely populated with various components, often in a complex 2.5D or 3D configuration. This requires extremely fine pitch interconnects and high accuracy alignment between different components.
System-in-package use multiple lithography steps to print the redistribution layers connecting the chips (RDLs), driving an increasing need in alignment and overlay metrology. Another limitation of conventional reticle driven lithography is that scaling is limited by die placement accuracy and warpage caused by the stacking of multiple chiplets and substrates. To address these limits in productivity and scaling, digital lithography for advanced packaging was introduced, to print the RDLs in the needed rotation to stich the interconnects to the packaged devices. To avoid cracking, delamination and voids, tighter inspection specs are needed. And to achieve high performing integrated system-in-package, new test steps are required to match chiplets in performance way ahead before sort, but the increasing I/O density requires contactless test as conventional probes become too large and cause defects as they perform test.
In this talk we will cover the Heterogenous Integration processes that drive the need to form an ecosystems of metrology inspection and test to fuel Moore’s law via high performance system-in-package
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