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Edge placement error (EPE) has become a critically important metric in semiconductor manufacturing. EPE quantifies the difference between the designed and printed layout of devices, coupling overlay and critical dimension (CD) of different litho layers. EPE consists of global and local components and can manifest itself between different physical layers of a device (e.g., via, metal) or within a single layer (primarily relevant for multi-patterning). This paper will study the simplest case of a single layer using an N10 litho-etch-litho-etch (LELE) metal layer patterning and will mainly cover global EPE. Monitoring and control of EPE will enable the stability of integrated circuit devices in advanced technology nodes. Inline EPE prediction in the process control loop at previous litho and etch steps enables early wafer status diagnosis and process disposition, which will improve process margin and wafer yield. Overlay and CD are essential inputs for EPE monitoring, prediction and control. Direct measurement of EPE on the device provides a reference value for an EPE model with overlay and CD measured on special targets. KLA’s pattern-centric solutions provide unique and accurate functionality in EPE metrology by analyzing SEM images on devices or targets in combination with the chip design. In this paper, we conduct experiments for EPE modeling and perform reference analysis using KLA’s pattern-centric solutions, targeting a higher pass rate of e-test, lower defectivity and targeted SEM inspection. KLA’s pattern-centric solutions are applied to e-beam images and provide die-to-database analysis by extracting measurements. The resultant EPE analysis can provide a higher correlation between electrical test data and targeted hotspot inspection, and can also be used to build the EPE model, for example, using e-overlay or CD targets. Overall, the results of these studies show good agreement with EPE model predictions and measured EPE by KLA’s pattern-centric solutions on device structures.
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