Implementing RISC-V processor with three-stage pipeline on FPGA

Zuo Qiao; Yujie Li; Wei Liang; Jianning Fan; Hongxu Ku; Xiaodong Zhang; Chong Shen

doi:10.1117/12.3034758

11 July 2024 Implementing RISC-V processor with three-stage pipeline on FPGA

Zuo Qiao, Yujie Li, Wei Liang, Jianning Fan, Hongxu Ku, Xiaodong Zhang, Chong Shen

Proceedings Volume 13210, Third International Symposium on Computer Applications and Information Systems (ISCAIS 2024); 1321033 (2024) https://doi.org/10.1117/12.3034758
Event: Third International Symposium on Computer Applications and Information Systems (ISCAIS 2023), 2024, Wuhan, China

Abstract

With the advent of the Internet of Things era, the demand for low-power, low-cost, scalable, open, and flexible chips is increasing day by day. This paper aims to design a RISC-V processor with a three-level pipeline structure, and verify its performance and functionality through verification on FPGA. The design process includes steps such as RTL design and simulation testing, RTL synthesis, constraints, Place and Route, burning, running program development and downloading, and running the built program on the RISC-V processor burned on FPGA. The kernel and peripheral design adopts a three-level pipeline design, and the functions and tasks of each stage are clearly described. The correctness and compliance of the design have been verified through waveform simulation and official testing. The design was ultimately validated on FPGA and performance analysis was conducted, indicating that the design can achieve ideal results in practical applications.

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Zuo Qiao, Yujie Li, Wei Liang, Jianning Fan, Hongxu Ku, Xiaodong Zhang, and Chong Shen "Implementing RISC-V processor with three-stage pipeline on FPGA", Proc. SPIE 13210, Third International Symposium on Computer Applications and Information Systems (ISCAIS 2024), 1321033 (11 July 2024); https://doi.org/10.1117/12.3034758

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KEYWORDS

Design

Field programmable gate arrays

Compliance

Combustion

Interfaces

Internet of things

Logic

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