Interline CCD imaging array with on-chip A/D conversion

Daniel J. Friedman; Woodward Yang

doi:10.1117/12.172772

1 May 1994 Interline CCD imaging array with on-chip A/D conversion

Daniel J. Friedman, Woodward Yang

Proceedings Volume 2172, Charge-Coupled Devices and Solid State Optical Sensors IV; (1994) https://doi.org/10.1117/12.172772
Event: IS&T/SPIE 1994 International Symposium on Electronic Imaging: Science and Technology, 1994, San Jose, CA, United States

Abstract

We describe an interline CCD imaging array which features high-speed, on-chip, parallel A/D conversion. In addition, we present test results from fabricated devices. The imaging chip was fabricated through MOSIS in a double-poly 2.0 micrometers CCD/CMOS technology on a chip with total area 2.25 mm X 2.22 mm. The chip is composed of a 28 X 39 pixel, interline imaging array, and a bank of 39 single-slope CCD/CMOS A/D converters; the converters function in parallel to achieve effective high-speed A/D conversion. Chip output is a stream of 8-bit digital data in which each 8-bit value corresponds to the light level at a pixel. Once an image has been captured, a set of parallel CCD shift registers transfer the data one column at a time to the parallel A/D converters. The analog data from each column is then converted in parallel and the resulting digital values are read out serially.

Citation Download Citation

Daniel J. Friedman and Woodward Yang "Interline CCD imaging array with on-chip A/D conversion", Proc. SPIE 2172, Charge-Coupled Devices and Solid State Optical Sensors IV, (1 May 1994); https://doi.org/10.1117/12.172772

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