Instruction systolic array in image processing applications

Manfred Schimmler; Hans-Werner Lang

doi:10.1117/12.248524

21 August 1996 Instruction systolic array in image processing applications

Manfred Schimmler, Hans-Werner Lang

Proceedings Volume 2784, Vision Systems: Sensors, Sensor Systems, and Components; (1996) https://doi.org/10.1117/12.248524
Event: Lasers, Optics, and Vision for Productivity in Manufacturing I, 1996, Besancon, France

Abstract

The ISATEC parallel computer is the first implementation of an instruction systolic array for the commercial market. The goal i\of integration of 1024 processors on an add-on-board for PCs has been achieved by the development of a low- power/low-area processor architecture whose instruction set is suited particularly for image processing applications. The paper introduces the concept of the instruction systolic array, its implementation and some application examples in the field of image processing.

Citation Download Citation

Manfred Schimmler and Hans-Werner Lang "Instruction systolic array in image processing applications", Proc. SPIE 2784, Vision Systems: Sensors, Sensor Systems, and Components, (21 August 1996); https://doi.org/10.1117/12.248524

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