Chip-scale 3D topography synthesis

Mariusz Niewczas; Xiaolei Li; Andrzej J. Strojwas; Wojciech P. Maly

doi:10.1117/12.310811

29 June 1998 Chip-scale 3D topography synthesis

Mariusz Niewczas, Xiaolei Li, Andrzej J. Strojwas, Wojciech P. Maly

Proceedings Volume 3334, Optical Microlithography XI; (1998) https://doi.org/10.1117/12.310811
Event: 23rd Annual International Symposium on Microlithography, 1998, Santa Clara, CA, United States

Abstract

We propose a novel approach to perform the chip scale mask to topography mapping by building a library of repetitive mask patterns. We call them vicinity patterns. They describe a collection of mask features in close proximity. This pattern library is used to synthesize 3-D topography of an arbitrary part of the chip topography. We define some process-related parameters, which we call critical interaction lengths, as a basis for mask decomposition into the vicinity patterns.

Citation Download Citation

Mariusz Niewczas, Xiaolei Li, Andrzej J. Strojwas, and Wojciech P. Maly "Chip-scale 3D topography synthesis", Proc. SPIE 3334, Optical Microlithography XI, (29 June 1998); https://doi.org/10.1117/12.310811

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