Paper
14 June 1999 Characterization and optimization of overlay target design for shallow-trench isolation (STI) process
Stephen Hsu, Jason K. Saw, Daniel R. Busath
Author Affiliations +
Abstract
This paper reports a systematic approach for characterizing and optimizing overlay target design to minimize the overlay target noise for shallow trench isolation (STI) process. Sixteen overlay targets were designed and evaluated to determine which target result in the most accurate and reproducible overlay measurements for STI process. The experiment conducted consists of two phase: the first phase is target screening for evaluating sixteen different target designs on STI laser. Each overlay target design is characterized by quantifying the mean TIS, TIS variability, target step height variance, dynamic precision , overlay measurement distribution, kernels signal and modeled residuals. Also, four one-layer inner and outer calibration targets were placed next to the sixteen targets to evaluate the CMP distortion effect on the overlay targets. In the second, phase, short and long-term gauge studies were performed. Stepper offset and correction were tested to verify the accuracy of overlay response. A design of experiment was completed to check robustness of overlay target to process variation in nitride thickness and CMP polishing time with and without the stepper alignment mark clear out process. Overlay measurement accuracy is correlated with SEM cross section to complete the evaluation.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Stephen Hsu, Jason K. Saw, and Daniel R. Busath "Characterization and optimization of overlay target design for shallow-trench isolation (STI) process", Proc. SPIE 3677, Metrology, Inspection, and Process Control for Microlithography XIII, (14 June 1999); https://doi.org/10.1117/12.350809
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CITATIONS
Cited by 3 scholarly publications.
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KEYWORDS
Overlay metrology

Optical alignment

Chemical mechanical planarization

Semiconducting wafers

Metrology

Polishing

Scanning electron microscopy

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