Design and implementation of an FPGA-based processor for compressed images

Venkataramanan S. Balakrishnan; Hardy Joseph Pottinger; Fikret Ercal; Mukesh Agarwal

doi:10.1117/12.403594

9 October 2000 Design and implementation of an FPGA-based processor for compressed images

Venkataramanan S. Balakrishnan, Hardy Joseph Pottinger, Fikret Ercal, Mukesh Agarwal

Proceedings Volume 4118, Parallel and Distributed Methods for Image Processing IV; (2000) https://doi.org/10.1117/12.403594
Event: International Symposium on Optical Science and Technology, 2000, San Diego, CA, United States

Abstract

This paper deals with the implementation of a systolic array architecture in hardware using FPGAs for processing compressed binary images without decompressing them. Specifically, run-length encoding (RLE) is used for compression. Processing images in compressed form provides a significant speedup in the computation. Using a systolic architecture and implementing it in hardware further increases the speed.

Citation Download Citation

Venkataramanan S. Balakrishnan, Hardy Joseph Pottinger, Fikret Ercal, and Mukesh Agarwal "Design and implementation of an FPGA-based processor for compressed images", Proc. SPIE 4118, Parallel and Distributed Methods for Image Processing IV, (9 October 2000); https://doi.org/10.1117/12.403594

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