Integration of active optical components typically serves five goals: enhanced performance, smaller space, lower power dissipation, higher reliability, and lower cost. We are manufacturing widely tunable laser diodes with an integrated high speed electro absorption modulator for metro and all-optical switching applications. The monolithic integration combines the functions of high power laser light generation, wavelength tuning over the entire C-band, and high speed signal modulation in a single chip. The laser section of the chip contains two sampled grating DBRs with a gain and a phase section between them. The emission wavelength is tuned by current injection into the waveguide layers of the DBR and phase sections. The laser light passes through an integrated optical amplifier before reaching the modulator section on the chip. The amplifier boosts the cw output power of the laser and provides a convenient way of power leveling. The modulator is based on the Franz-Keldysh effect for a wide band of operation. The common waveguide through all sections minimizes optical coupling losses. The packaging of the monolithically integrated chip is much simpler compared to a discrete or hybrid solution using a laser chip, an SOA, and an external modulator. Since only one optical fiber coupling is required, the overall packaging cost of the transmitter module is largely reduced. Error free transmission at 2.5Gbit/s over 200km of standard single mode fiber is obtained with less than 1dB of dispersion penalty.

The packaging of optical components (splitters, WDM, VOA, switches) used in telecommunication applications uses very often Fiber Arrays: it is indeed a very practical component to connect high channel count components (from 1 to 48 channels typically) to the outside world. These Fiber Arrays can be in different formats: standard, focusing, collimating, with single mode fiber or polarization maintaining fiber. But the optical performance of the packaged component is primarily linked to the performance of the Fiber Array. Also, the reliability of the packaged component is mainly determined by the reliability of the Fiber Array, and the way it is attached to the component. The optical performance includes mainly the fiber position error (Core Offset), which determines the insertion loss, but also the polishing induced parameters: polishing angles, surface planarity, fiber protrusion. Optical parameters are also important: excess loss, PDL, and return loss. During the presentation will be related some measurement options, and some results. The reliability of the fiber array is also very important, in order to meet the Telcordia qualification on the packaged product. Unfortunately, these standards, which apply to the packaged component, does not describe qualification procedures for Fiber Arrays, leaving some uncertainty on how to assess the reliability of the product. Different qualification options will be discussed, and some Telcordia qualification results shown.

Integrated 3-D Micro-Optical Interconnection System Chip-level optical interconnects is an alternative technology that offers the ability to potentially overcome the interconnect bottleneck projected to occur in high-end computing and telecommunication systems. In this context, we are investigating a fused 3-D micro-optical architecture that enables through-wafer vertical optical interconnects. Based on this architecture a prototype 3-D micro-optical interconnection system is fabricated that is scaleable and can be easily modified to implement various optical interconnect configurations. This prototype consists of an integrated optoelectronic transmitter and receiver multichip module. A diffractive optical element is used for optically interconnecting the multichip modules and in establishing a point-to-point link. The link length, as measured from the optical source of the transmitter to the detector plane of the receiver is 2.332 mm. The transmitter and receiver module dimensions as well as the integrated system volume are a meager 2.9x3.3 mm2, 2.1x2.7 mm2, and 15.27mm3, respectively, and preserve the VLSI-scale. The design, fabrication, integration of this system, and experimental results are presented.

In fiber-optic component attachment using laser welding, the welding-induced-alignment-distortion (WIAD) is an issue significantly affecting the packaging yield. Our previous investigation has shown that an elimination or minimization of WIAD is possible if the relevant laser welding process parameters such as welding sequence can be optimized. In this work, a more realistic physics based laser welding model is introduced and incorporated into our finite element analysis model by a few user subroutines, the effect of welding sequence on WIAD in a butterfly laser diode module package is evaluated. The result verifies the conclusion that the effect of laser welding sequence on WIAD for butterfly laser diode packages is significant and WIAD control can be achieved as appropriate welding sequence is employed.

A process for flexible, scalable photonic manufacturing is described. Optical components are actively pre-aligned and secured to precision mounts. In a subsequent operation, the mounted optical components are passively placed onto a substrate known as an Optical Circuit Board (OCB). The passive placement may be either manual for low volume applications or with a pick-and-place robot for high volume applications. Mating registration features on the component mounts and the OCB facilitate accurate optical alignment. New photonic circuits may be created by changing the layout of the OCB. Predicted yield data from Monte Carlo tolerance simulations for two fiber optic photonic circuits is presented.

Photonics packaging applications require significantly higher precision die bonding processes than traditional electronics and RF/microwave devices. Die placement accuracy of microns and better has been demonstrated. Key factors affecting the capability ofplacing die at accuracies of 5microns in photonics packaging are discussed. Factors that enable high accuracy die bonding range from machine platform design to a combination ofprocess parameters. Another key factor in die bonding placement accuracy is the quality of visual reference points or fiducials on the die, substrate, or surrounding package. Examples ofgood and poor visual references are shown and a discussion ofdie and package design is presented. A method ofplacement accuracy validation and a discussion ofhigh accuracy die bonding applications are presented.

The thermal instability of central wavelength of AWG is analyzed theoretically. The analysis reveals that waveguide dispersion caused by temperature fluctuation of AWG is the primary source of the thermal instability whereas the thermal instability due to photo-elastic effect and thermal expansion of waveguides is comparatively small.

With the increasing demand for solving more complex problems, high-performance multiprocessing systems are attracting more and more research efforts. One of the challenges is to effectively support the communications among the processes running in parallel on the multiprocessors. Due to the physical limitations of electrical interconnects, interconnection networks impose a potential bottleneck limiting the overall performance. On the other hand, optics has many advantages as an interconnect technology. In this paper, benefits of optics are evaluated along with a comparison of two mainstream system topologies, shared bus and switched media. This analysis leads to an innovative interconnect architecture, optical centralized shared bus. The crucial design aspects of this architecture, including system organization, working principle, and conversion between free-space propagation and substrate-guided mode propagation by using volume holographic gratings, are delineated. To ensure the feasibility of using this architecture as high ­performance interconnection networks in real multiprocessing systems, a PCI implementation of the centralized shared memory multiprocessor system is proposed. In this prototype, the required connectivity is accomplished by using the optical centralized shared bus architecture. Some preliminary results are presented.

We demonstrated a new architecture of the optical interconnection system which can be applied in the waveguide-embedded optical printed circuit board (PCB). We used 45° ended optical connection rods as a medium to guide light paths perpendicularly between surface-emitting lasers (or photodiode) and waveguides. A polymer film of multimode waveguides with cores of 100μm x 65μm was sandwiched between conventional PCBs. We made through-holes with a diameter of ~140μm on the PCB, passing through the waveguide cores, using Ti-sapphire laser drill. The optical rods were made of the segment of multimode silica fiber ribbon. One end of the fiber segment was cut with 45° and the other end with 90° by using the high power laser cutting technique. These fiber rods were inserted into the through-holes formed in the PCB, adjusting the insertion depth to locate the 45°-end of rods near the waveguide core. From this interconnection system, we achieved 12channels optical transmission link through a waveguide with a channel pitch of 250μm in the optical PCB. This new interconnection structure using the optical connection rods is well compatible with the fabrication processes of conventional electronic PCB which is employing the through-hole formation by laser drill and the lamination of plastic films by compression.

A novel photonic switching network with vertical cavity surface emitting laser (VCSEL) array packaging for parallel multiprocessor cluster system is described. The parallel multiprocessor cluster system provides 64 serve nodes connected by photonic switching network with parallel optical links. There are eight cluster subsystems in the system. Each subsystem includes eight computing nodes and an optical interconnect backplane of 8x8 crossbar optical interconnection network with VCSEL-based optoelectronic I/O parallel interface. Every I/O parallel interface between optical interconnection network and every computing node includes 16 VCSEL emitter pixels, 16 PIN receiver pixels. In order to couple 16 signal light beam array into optical fiber array ribbon, a fabrication technique based on the high precise position slot is used for assembling optical fiber array interface. A packaging structure for optical fiber array interface is presented. As the position slots of optical fiber array interface are formed by VLSI photolithography and IcP etch techniques, and etching depth is smaller compared with V-groove slot, the high precision slots with 25Ojtm pitch can be obtained. A configuration of coupling packaging for 16 VCSEL pixel array to 16 fiber array with 45° end surface is also presented in this paper.

We report on a polymer-on-silicon optical bench platform that enables the hybrid integration of elemental passive and active optical functions. Planar polymer circuits are produced photolithographically, and slots are formed in them for the insertion of chips and films of a variety of materials. The polymer circuits provide interconnects, static routing elements such as couplers, taps, and multi/demultiplexers, as well as thermo-optically dynamic elements such as switches, variable optical attenuators, and tunable notch filters. Crystal-ion-sliced thin films of lithium niobate are inserted in the polymer circuit for polarization control or for electro-optic modulation. Films of yttrium iron garnet and neodymium iron boron magnets are inserted in order to magneto-optically achieve non-reciprocal operation for isolation and circulation. Indium phosphide and gallium arsenide chips are inserted for light generation, amplification, and detection, as well as wavelength conversion. The functions enabled by this multi-material platform span the range of the building blocks needed in optical circuits, while using the highest-performance material system for each function. We demonstrated complex-functionality photonic components based on this technology, including a metro ring node module and a tunable optical transmitter. The metro ring node chip includes switches, variable optical attenuators, taps, and detectors; it enables optical add/drop multiplexing, power monitoring, and automatic load balancing, and it supports shared and dedicated protection protocols in two-fiber metro ring optical networks. The tunable optical transmitter chip includes a tunable external cavity laser, an isolator, and a high-speed modulator.

Fabrication of optical waveguides by a simple patterning process using photosensitive polyimide (PSPI) is described. Light waveguide based on PSPI was fabricated by photolithographic processing without use of dry etching process. The PSPI varnish is comprised of polyamic acid (PAA) which was made from fluorinated diamine and fluorinated tetracarboxylic dianhydride, and photosensitizer. The PSPI has the following characteristics: glass transition temperature (Tg) of 330 °C, coefficient of thermal expansion of 40 ppm/K. Moreover the PSPI is colorless, and posses low absorption at 1 .3 and 1 .55im. The sidewalls and the surfaces ofthe fabricated waveguide are very smooth, which is essential for the low loss optical mode propagation and lower scattering of the mode due to the imperfections. Single and multimode buried ridge waveguides on quartz glass substrate were fabricated and tested. Optical propagation losses were measured by standard cut back method and found to be as low as 0.4 dB/cm @ 1.55 jim. This fabrication process would be expected to contribute to low cost production for high performance opto-electronic devices.

Optical switches based on deflection of a waveguide element offer low crosstalk, low polarization dependency, low power consumption, and high degree of integration. Such switches made by post processing of polymeric waveguides onto MEMS structures of silicon-on-insulator (SOI) efficiently combine low loss waveguides with the exceptional mechanical properties of single crystalline silicon. An important aspect of this concept is that it allows independent optimization of the mechanical and optical structures by efficiently separating the two. Well established, high yield methods exist for structuring silicon based on deep reactive ion etching (DRIE), which allows the formation of mechanical structures with high aspect ratio. The mechanical structure can then be planarized for further processing by utilizing spin coating properties of certain polymers. This allows post processing of high-resolution passive polymeric waveguide networks that can fulfil a variety of functions depending on the application, including spot-size transformers for low loss coupling to optical fibers. These waveguides can also potentially be integrated with CMOS or active optoelectronic elements into forming highly functional hybrid photonic integrated circuits, partly facilitated by the low temperatures required for processing of polymers. This paper highlights key process technologies and specifically discusses issues related to an optical switch that was developed for proof of concept. This switch was made of 5μm thick SOI with 3μm wide, high optical confinement polymeric waveguides. Switching times were down to 30μs, switching voltages 20 to 50V, and crosstalk was -32dB. The paper further outlines possible applications of the switch to state-of-the-art problems in photonics.

VLSI/ULSI and the evolutions being driven by the International Technology Roadmap for Semiconductors (ITRS) are once again presenting severe challenges to the metal interconnect. Clock skew and other timing delays are becoming application critical design factors. The RC induced delays as well as parasitics (due to the trace density) are causing severe limitations to designs. Unfortunately these issues are very difficult to deal with using conventional computer aided design tools although efforts are being made, notably via DARPA funded programmes. We shall review techniques (and design elements) for on-chip optical communications. Through this we will present a new proposition for optical interconnects integrated upon otherwise conventional CMOS devices. We believe that the illustrated methodologies can be developed to provide very effective optical functionality appropriate to alleviating high-speed communications and timing issues.

We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

We have integrated several optoelectronic devices into deep-submicron silicon fabrication process. The main results for monolithic integration of silicon planar interdigitated P-I-N photodiodes with transimpedance amplifiers and waveguide grating couplers will be reviewed. The integration process was carried out in an unmodified 130nm CMOS process flow, on SOI substrates. Photodetectors that were fabricated on 200nm-thick SOI exhibited a 3dB electrical bandwidth of 10GHz for -5V bias while the photodetectors fabricated on 2000nm-thick SOI had 8GHz 3dB electrical bandwidth for -28V bias. The external quantum efficiency of the 2000nm-thick photodetectors at 835nm was 14%. The 200nm-thick photodetectors were integrated with waveguide grating couplers. For 835nm, the external quantum efficiency of the photodetector improved from 3% to 12% when a diffraction grating with 265nm period was integrated on top of the photodiode. The 3dB electrical bandwidth of these photodetectors was 4.1GHz (RC limited). The dark current for these devices was 10pA at -3V bias for an area of 2500mm2. The photodetectors fabricated on 2000nm-thick SOI substrates were wire-bonded to SiGe transimpedance amplifiers with 184W transimpedance gain. When the photodiode was used in avalanche operation mode the sensitivity of -7dBm (BER<10-9) was achieved at 10Gb/s. The multiplication gain for the avalanche photodetector was in this case M=4. This is the highest speed reported for an all-silicon optical receiver.

The principles of operation and general design criteria for PIN diode variable optical attenuators (VOAs) realized from silicon-on-insulator rib waveguide structures are described. We present as a benchmark the performance of devices based on the established VOA produced by Bookham Technology Plc, and demonstrate 25dB attenuation at less than 70mW with novel recessed dopant geometries. Optical and electrical simulation results for new, smaller cross-section VOA structures based on rib waveguides utilizing a 2mm high guiding layer are detailed and discussed. Experimental results demonstrating the successful fabrication of these structures and the significant improvements in performance attained are presented. In particular we show that the attenuation efficiency can be 30% higher than that of the larger structure, and that modulation bandwidths may approach 10MHz.

Steps are described for fabricating, preparing, and assembling pigtailed optical mode converters being developed for low loss coupling of optical fibers to high index contrast waveguide devices and arrays. The mode converters comprise adiabatic waveguide tapers fabricated from silicon-on-insulator (SOI) wafers, utilizing the silicon device layer as a waveguide core and the buried oxide as the underlying clad. Polished facets comprise the input and output ends of the tapers. The mode shape at the input typically matches that of an SMF-28 fiber, while the output ends can be sized to match various waveguide device mode shapes, typically ranging from 1 to 5 microns with aspect ratios as high as 5:1. Semiconductor planar processing techniques are employed to form the tapers upon commercial SOI wafers. An additional oxide layer is deposited upon the tapers to provide a symmetric clad around the silicon. Once fabricated, the wafers are diced into chips containing rows of tapers. The input and output facets are then lapped and polished, using a precision end point process, after which an anti reflective (AR) coating is applied. Following AR coating the chips are aligned and bonded to either single fibers or V-groove fiber arrays, creating the final pigtailed mode converter device. The insertion loss for completed mode converters ranges from 0.5 to 1 dB depending upon output facet size and asymmetry.

We present a novel type of grating-assisted coupler for coupling light from an optical fibre to a thin semiconductor waveguide. The Dual Grating-Assisted Directional Coupler (DGADC) consists of two gratings, one thick waveguide with a refractive index similar to the refractive index of the fibre, a thin semiconductor waveguide and a layer with refractive index which is between that of the thick and thin waveguides. Specifically, a coupler in silicon on insulator (SO!) has been analysed. The maximum coupling efficiency for this coupler can approach 1 00%, while the minimum coupling length can be around 2mm.

The high index contrast of silicon-on-insulator (SOI) enables the scaling down of planar waveguide components into the microphotonic regime, but has the unwanted consequence of inducing a large TE-TM polarization birefringence. For ridge waveguides this birefringence can be reduced to an acceptable level by using appropriate ridge dimensions [1], but with decreasing Si thickness the required fabrication tolerances quickly become too narrow to implement this solution. Components with slab waveguide regions such as echelle grating demultiplexers cannot be made polarization independent using this method. An alternate approach is to introduce a polarization compensation region in the combiner section of an AWG or echelle grating to eliminate the polarization dependent wavelength shift[2]. In its original implementation, the compensator is fabricated by changing the local waveguide thickness. The resulting birefringence correction can be sensitive to errors in etch depth, and the mode mismatch between compensator and slab waveguide sections is a source of approximately 1 dB extra insertion loss (IL) for SOI demultiplexers with Si waveguide thickness in the range from 2 to 5 m. We describe a new compensator structure for the SOI platform using a buried low index layer, in this case SiO2 sandwiched between the Si waveguide layer and another Si cap layer. Such a silicon-oxide-silicon (SOS) compensator on SOI can eliminate the TE-TM wavelength shift of an SOI AWG or echelle grating demultiplexer without introducing a significant mode mismatch between the compensator and slab waveguide sections. A demultiplexer with an SOS compensator has almost 1 dB lower insertion loss of an equivalent device with an etched compensator. The SOS compensator is easily implemented using standard oxide and a-Si or polysilicon deposition techniques. In this paper we present calculations and experimental results on the effective birefringence compensation, PDL and IL of SOS compensators in SOI waveguide demultiplexers.

Silicon-based optical modulators are expected to be important components in some optical networks. The optical modulation mechanism can be achieved either via the plasma dispersion effect, or by thermal means. Both are relatively slow processes when utilized in large (multi micron) waveguide structures, which researchers tend to concentrate on for ease of coupling. Using large waveguide structures limits the operating speed and hence excludes the applicability of these devices in areas where higher speeds are required. This limitation could be overcomed by using smaller waveguides (of the order of 1Rm). In this paper, we present the basic operating mechanism, design, and fabrication details of an optimum three terminal p-i-n diode based optical phase modulator based on Silicon-On-Insulator (501). The device was optimised via electrical and optical modeling and is predicted to operated at 1 .3GHz with a power reduction of900%, as compared to previously published designs.

Inadequate performance of interconnects in emerging integrated circuitry has generated a need for alternative signal transmission solutions. Integration of dense arrays of high frequency III-V photoemitters and photodetectors with Si platform is one of the challenging tasks. Comparison of monolithic and hybrid integration technologies highlights the advantages of hybrid approaches at least for emitters highly sensitive to growth defects. A novel protocol for fabrication of III-V optoelectronic components such as LEDs, VCSELs and photodetectors on Si platform is proposed. The simulations of thermal behavior and mechanical stresses of this integration scheme was performed using finite element analysis and revealed adequate heat dissipation. Simulations show that this protocol allows to reduce overheating and mechanical stresses to enhance the optoelectronic devices performance and increase their lifetime. The III-V structures are grown homoepitaxialy on GaAs substrate, then bonded to a Si wafer using low-temperature polymer followed by wet etching of the substrate. The scheme involves VCSEL processing with coplanar metallization on Si with PMGI reflow planarization. MBE-grown reversed VCSEL structure was used for manufacturing of the test devices using this novel protocol. An AlAs etch stop layer was imbedded into the structure. 10 um thick VCSEL structure was bonded on Si using BCB (CycloteneTM). Substrate was completely removed by selective etching to reduce thermal stresses to enhance the optoelectronic devices performance and increase their lifetime. The array of the 3D devices was fabricated using wet etching. A 10 um-thick high frequency VCSEL with coplanar metallization is processed on Si with PMGI reflow planarization. Electro-luminescence spectrum, I-V and P-T characteristics were measured and compared with a reference structure. It was found that measured thermal impedance is about five times higher than for devices on a host GaAs wafer. Simulation of thermal behavior was done for bonded and non-bonded structure. It was found that measured values of thermal impedance are in good agreement with simulation results.

Silicon is the leading material concerning high-density electronic functionality. Integration and economy of scale are the two keys ingredients for the silicon technological success. The present interconnection degree is sufficient to cause interconnect propagation delays, overheating and information latency between single devices. The overcome of this Interconnection bottleneck is together the main motivation and opportunity for the present-day silicon microphotonics, where attempts to combine photonic and electronic components on a single Si chip or wafer are strongly pursued. The main limitation of this technology when is implemented in silicon is the lack of any practical silicon light sources: either an efficient LEDs or a Si lasers. Despite of all, during these last 10 years many different strategies have been employed to overcome these materials limitations and silicon light emitting diodes (LED) are now only a factor of ten out of the severe market requirements. The main future challenge for silicon microphotonics is the demonstration of a silicon-based laser action to engineer a silicon laser. During the nineties many research efforts have been focused to this goal. A steady improvement in silicon LED performances has been achieved. However it was only at the end of 2000 and during 2001 that many breakthroughs have been demonstrated showing that this field is very active and still promising. The up to now principal approaches can be subdivided into the following categories: 1. Bulk silicon with extremely high non-radiative lifetime 2. Silicon nanocrystals 3. Doping of silicon with rare earths ions 4. Direct band-gap group IV alloys and quantum confined Si or Ge or group IV alloy structures 5. Quantum cascade Si/Ge structures During the presentation a critical review of all these approaches will be performed and the most suitable candidate will be underlined.

It is well documented that optical sensors offer many advantages over conventional electronic devices for some applications because they are more versatile, lighter, smaller, immune to electrical interference and can be densely multiplexed. However, to date, many optical sensor instrument systems have been insufficiently robust for use in harsh environments and relatively expensive due to the use of discrete optical components. Hence the primary aim of this work is to develop a physically robust and cost effective interrogation system for fibre Bragg grating strain sensors by integrating a system on a silicon chip. Therefore it will be possible to replace many of the costly discrete components. Related improvements will be the reduction of size and weight, an increase in robustness, and performance in relatively harsh environments. This work will focus on the development of a Micro Electro Mechanical System (MEMS) tunable Fabry-Perot optical filter, together with an integrated optical circuit fabricated on silicon-on-insulator (SOT) to deliver the signal to the Bragg gratings and to detectors based in the same optical circuit. In this paper we discuss the requirements for integration, as well as reviewing the principles of strain measurement using fibre Bragg gratings. The latter will include a brief discussion of the merits of multiplexing via single or multiple fibres

Epitaxial lateral overgrowth of (ELO) InP on (001) InP/Si substrate is explored in a low pressure hydride vapor phase epitaxy system under various growth conditions. The effect of gas phase supersaturation on boundary plane formation of ELO and the behavior of dislocations in the grown layers are investigated. We found that the growth rate on (1 1 1)A boundary plane is determined by Burton-Cabrera-Frank model, which predicts a parabolic relationship between gas phase supersaturation and growth rate. Formation of (1 1 1)A plane will cause stacking faults in the grown InP layer. They will interact and annihilate each other and introduce fresh dislocations during the growth. Gas phase supersaturation can also be changed by varying opening separation distance. Low gas phase supersaturation is obtained by decreasing the distance between two openings. It gives rise to a lower staking fault density due to the suppression of nucleation of { 1 1 1 } facet plane at the edge of ELO. Etch pit density (EPD) and X-ray diffraction (XRD) techniques are used to estimate the dislocation density. Full width at half maximum of rocking curve at (004), (115) and (117) reflections were used to calculate the dislocation density in ELO InPISi. Experimentally measured etch pit density is smaller than the dislocation density derived from XRD data. In general the dislocation density is dependent on gas phase supersaturation. In this work, we demonstrate that it is possible to grow high quality InP layer on silicon substrate by epitaxial lateral overgrowth technique under optimized growth conditions.

An integrated optical strain sensor based on a silicon-on-insulator (SOI) optical waveguide Mach-Zehnder interferometer has been demonstrated. The common problem of cross sensitivity to temperature changes has been greatly reduced by designing the lengths of the two interferometer arms to be exactly equal, in the absence of strain, so that thermally induced changes in the optical path lengths cancel out in the interference signal. The waveguide path in both arms of the interferometer has a long straight section and is folded back by a 180 degree bend. The straight section in one arm is perpendicular to that in the other arm so that the symmetry in the optical path lengths is broken when the applied strain in these two orthogonal directions is different. The interferometer output is thus a measure of the difference in strain along these two directions. For the initial device, the interferometer's size was approximately 15 x 15 mm, with the straight sections in each of the two arms being 12 mm long. For TM polarized light at a wavelength of 1.55 microns, the interferometer output intensity was observed to vary sinusoidally with applied uniaxial strain at a rate of 10 degrees per microstrain. This is in good agreement with the theoretical prediction. The strain sensitivity, as limited by system noise, was below one microstrain. SOI is an ideal material choice for this device. It is suitable for passive fiber alignment using V-groove techniques, and the ability to use small waveguide bending radii makes possible sensors that are more compact than has been demonstrated here.