A 0.35-µm CMOS 17-bit@40-kS/s cascade 2-1 sigma-delta modulator with programmable gain and programmable chopper stabilization

Oscar Guerra; Sara Escalera; Jose M. de la Rosa; Rocio del Rio; Fernando Medeiro; Angel Rodriguez-Vazquez

doi:10.1117/12.608304

30 June 2005 A 0.35-μm CMOS 17-bit@40-kS/s cascade 2-1 ΣΔ modulator with programmable gain and programmable chopper stabilization

Oscar Guerra, Sara Escalera, Jose M. de la Rosa, Rocio del Rio, Fernando Medeiro, Angel Rodriguez-Vazquez

Author Affiliations +

Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608304
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain

Abstract

This paper describes a 0.35μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade ΣΔ modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator includes a programmable set of gains (x0.5, x1, x2, and x4) and a programmable set of chopper frequencies (fs/16, fs/8, fs/4 and fs/2). It has also been designed to operate within the restrictive environmental conditions of automotive electronics (-40°C, 175°C). The modulator architecture has been selected after an exhaustive comparison among multiple ΣΔΜ topologies in terms of resolution, speed and power dissipation. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12MHz and consumes, all together, 14.7mW from a single 3.3-V supply. Experimental measurements result in 99.77dB of Dynamic Range (DR), which combined with the gain programmability leads to an overall DR of 112dB. This puts the presented design beyond the state-of-the-art according with the existing bibliography.

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Oscar Guerra, Sara Escalera, Jose M. de la Rosa, Rocio del Rio, Fernando Medeiro, and Angel Rodriguez-Vazquez "A 0.35-μm CMOS 17-bit@40-kS/s cascade 2-1 ΣΔ modulator with programmable gain and programmable chopper stabilization", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608304

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