Paper
27 November 2007 The challenges of transitioning from linear to high-order overlay control in advanced lithography
M. Adel, P. Izikson, D. Tien, C. K. Huang, J. C. Robinson, B. Eichelberger
Author Affiliations +
Abstract
In the lithography section of the ITRS 2006 update, at the top of the list of difficult challenges appears the text "overlay of multiple exposures including mask image placement". This is a reflection of the fact that today overlay is becoming a major yield risk factor in semiconductor manufacturing. Historically, lithographers have achieved sufficient alignment accuracy and hence layer to layer overlay control by relying on models which define overlay as a linear function of the field and wafer coordinates. These linear terms were easily translated to correctibles in the available exposure tool degrees of freedom on the wafer and reticle stages. However, as the 45 nm half pitch node reaches production, exposure tool vendors have begun to make available, and lithographers have begun to utilize so called high order wafer and field control, in which either look up table or high order polynomial models are modified on a product by product basis. In this paper, the major challenges of this transition will be described. It will include characterization of the sources of variation which need to be controlled by these new models and the overlay and alignment sampling optimization problem which needs to be addressed, while maintaining the ever tightening demands on productivity and cost of ownership.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
M. Adel, P. Izikson, D. Tien, C. K. Huang, J. C. Robinson, and B. Eichelberger "The challenges of transitioning from linear to high-order overlay control in advanced lithography", Proc. SPIE 6827, Quantum Optics, Optical Data Storage, and Advanced Microlithography, 682722 (27 November 2007); https://doi.org/10.1117/12.778457
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CITATIONS
Cited by 6 scholarly publications.
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KEYWORDS
Data modeling

Semiconducting wafers

Overlay metrology

Scanners

Reticles

Lithography

Metrology

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