Electrical validation of through process OPC verification limits

Omprakash Jaiswal; Rakesh Kuncha; Taksh Bharat; Vipin Madangarli; Edward Conrad; James Bruce; Sajan Marokkey

doi:10.1117/12.846572

1 April 2010 Electrical validation of through process OPC verification limits

Omprakash Jaiswal, Rakesh Kuncha, Taksh Bharat, Vipin Madangarli, Edward Conrad, James Bruce, Sajan Marokkey

Proceedings Volume 7638, Metrology, Inspection, and Process Control for Microlithography XXIV; 76380U (2010) https://doi.org/10.1117/12.846572
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

Electrical validation of through process OPC verification limits in 32nm process technology is presented in this paper. Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence of each process conditions. The design of electrical layouts is extended to sub ground rules to force failure and derive better correlation between electrical and simulated outputs. Some of these sub ground rule designs amplify the failures induced by exposure tool, such as optical aberrations. Observations in this regard will be reported in the paper. Sensitivity with respect to dimensions, orientations and wafer distribution will be discussed in detail.

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Omprakash Jaiswal, Rakesh Kuncha, Taksh Bharat, Vipin Madangarli, Edward Conrad, James Bruce, and Sajan Marokkey "Electrical validation of through process OPC verification limits", Proc. SPIE 7638, Metrology, Inspection, and Process Control for Microlithography XXIV, 76380U (1 April 2010); https://doi.org/10.1117/12.846572

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KEYWORDS

Electrical breakdown

Failure analysis

Optical proximity correction

Semiconducting wafers

Lithography

Optical simulations

Process modeling

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