45nm transistor variability study for memory characterization

Kun Qian; Costas J. Spanos

doi:10.1117/12.846704

2 April 2010 45nm transistor variability study for memory characterization

Kun Qian, Costas J. Spanos

Proceedings Volume 7641, Design for Manufacturability through Design-Process Integration IV; 76410G (2010) https://doi.org/10.1117/12.846704
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

We have previously analyzed spatial process variation using 45nm ring oscillator arrays. Our hierarchical variability model had proven to be very useful in revealing interesting systematic patterns, and in separating them from native random variability. To further understand the underlying mechanism of the process variation, we continue to work on the analysis and modeling of spatial variation of transistors made on the same 45nm technology test chips. A novel statistical compact device modeling procedure is used to extract the systematic and random variation of device parameters across wafer and within die. Statistical SPICE simulation is then performed based on the extracted variation model of device parameters. The results compare well with actual ring oscillator and SRAM measurements, in that the characteristic systematic, spatial and random patterns have been captured for circuit-level simulation.

Citation Download Citation

Kun Qian and Costas J. Spanos "45nm transistor variability study for memory characterization", Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 76410G (2 April 2010); https://doi.org/10.1117/12.846704

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