Diffraction-based overlay for spacer patterning and double patterning technology

Byoung Hoon Lee; JeongSu Park; Jongsu Lee; Sarohan Park; ChangMoon Lim; Dong-Gyu Yim; Sungki Park; Chan-Ho Ryu; Stephen Morgan; Maurits van de Schaar; Andreas Fuchs; Kaustuve Bhattacharyya

doi:10.1117/12.870473

20 April 2011 Diffraction-based overlay for spacer patterning and double patterning technology

Byoung Hoon Lee, JeongSu Park, Jongsu Lee, Sarohan Park, ChangMoon Lim, Dong-Gyu Yim, Sungki Park, Chan-Ho Ryu, Stephen Morgan, Maurits van de Schaar, Andreas Fuchs, Kaustuve Bhattacharyya

Author Affiliations +

Proceedings Volume 7971, Metrology, Inspection, and Process Control for Microlithography XXV; 79712U (2011) https://doi.org/10.1117/12.870473
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States

Abstract

Overlay performance will be increasingly important for Spacer Patterning Technology (SPT) and Double Patterning Technology (DPT) as various Resolution Enhancement Techniques are employed to extend the resolution limits of lithography. Continuous shrinkage of devices makes overlay accuracy one of the most critical issues while overlay performance is completely dependent on exposure tool. Image Based Overlay (IBO) has been used as the mainstream metrology for overlay by the main memory IC companies, but IBO is not suitable for some critical layers due to the poor Tool Induced Shift (TIS) values. Hence new overlay metrology is required to improve the overlay measurement accuracy. Diffraction Based Overlay (DBO) is regarded to be an alternative metrology to IBO for more accurate measurements and reduction of reading errors. Good overlay performances of DBO have been reported in many articles. However applying DBO for SPT and DPT layers poses extra challenges for target design. New vernier designs are considered for different DPT and SPT schemes to meet overlay target in DBO system. In this paper, we optimize the design of the DBO target and the performance of DBO to meet the overlay specification of sub-3x nm devices which are using SPT and DPT processes. We show that the appropriate vernier design yields excellent overlay performance in residual and TIS. The paper also demonstrated the effects of vernier structure on overlay accuracy from SEM analysis.

Citation Download Citation

Byoung Hoon Lee, JeongSu Park, Jongsu Lee, Sarohan Park, ChangMoon Lim, Dong-Gyu Yim, Sungki Park, Chan-Ho Ryu, Stephen Morgan, Maurits van de Schaar, Andreas Fuchs, and Kaustuve Bhattacharyya "Diffraction-based overlay for spacer patterning and double patterning technology", Proc. SPIE 7971, Metrology, Inspection, and Process Control for Microlithography XXV, 79712U (20 April 2011); https://doi.org/10.1117/12.870473

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