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4 April 2012 Inspection and metrology for through-silicon vias and 3D integration
Andrew C. Rudack
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Proceedings Volume 8324, Metrology, Inspection, and Process Control for Microlithography XXVI; 832403 (2012) https://doi.org/10.1117/12.920301
Event: SPIE Advanced Lithography, 2012, San Jose, California, United States
Abstract
3D IC integration employs advanced interconnect technologies including through-silicon vias (TSVs), bonding, wafer thinning, backside processing and fine pitch multi-chip stacking. In 2013, Mobile Wide I/O DRAM is expected to be one of the first high volume 3D IC applications. Many of the manufacturing steps in TSV processing and 3D integration can complicate inspection and metrology. This paper reviews a typical via-mid flow emphasizing the inspection and metrology challenges inherent in 3D integration. A preliminary look at the 2011 ITRS roadmap for 3D interconnect metrology is presented, including the gaps in currently available inspection and metrology tools.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
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Andrew C. Rudack "Inspection and metrology for through-silicon vias and 3D integration", Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 832403 (4 April 2012); https://doi.org/10.1117/12.920301
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Cited by 3 scholarly publications and 1 patent.
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KEYWORDS
Semiconducting wafers
3D metrology
Metrology
Inspection
Wafer bonding
Copper
Microscopes
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