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To realize HVM (High Volume Manufacturing) with CP (Character Projection) based EBDW, the shot count
reduction is the essential key. All device circuits should be composed with predefined character parts and we call this
methodology “CP element based design”. In our previous work, we presented following three concepts [2].
1) Memory: We reported the prospects of affordability for the CP-stencil resource.
2) Logic cell: We adopted a multi-cell clustering approach in the physical synthesis.
3) Random interconnect: We proposed an ultra-regular layout scheme using fixed size wiring tiles containing repeated
tracks and cutting points at the tile edges.
In this paper, we will report the experimental proofs in these methodologies.
In full chip layout, CP stencil resource management is critical key. From the MCC-POC (Proof of Concept) result [1],
we assumed total available CP stencil resource as 9000um2. We should manage to layout all circuit macros within this
restriction. Especially the issues in assignment of CP-stencil resource for the memory macros are the most important as
they consume considerable degree of resource because of the various line-ups such as 1RW-, 2RW-SRAMs, Resister
Files and ROM which require several varieties of large size peripheral circuits. Furthermore the memory macros
typically take large area of more than 40% of die area in the forefront logic LSI products so that the shot count increase
impact is serious. To realize CP-stencil resource saving we had constructed automatic CP analyzing system. We
developed two types of extraction mode of simple division by block and layout repeatability recognition. By properly
controlling these models based upon each peripheral circuit characteristics, we could minimize the consumption of CP
stencil resources. The estimation for 14nm technology node had been performed based on the analysis of practical
memory compiler. The required resource for memory macro is proved to be affordable value which is 60% of full CP
stencil resource and wafer level converted shot count is proved to be the level which meets 100WPH throughput.
In logic cell design, circuit performance verification result after the cell clustering has been estimated. The cell
clustering by the acknowledgment of physical distance proved to owe large penalty mainly in the wiring length. To
reduce this design penalty, we proposed CP cell clustering by the acknowledgment of logical distance.
For shot-count reduction of random interconnect area design, we proposed a more structural routing architecture which
consists of the track exchange and the via position arrangement. Putting these design approaches together, we can design
CP stencils to hit the target throughput within the area constraint.
From the analysis for other macros such as analog, I/O, and DUMMY, it has proved that we don’t need special CP
design approach than legacy pattern matching CP extraction.
From all these experimental results we get good prospects to the reality of full CP element based layout.
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