10 April 2015 Patterning critical dimension control for advanced logic nodes
Bertrand Le-Gratiet, Jean De-Caunes, Maxime Gatefait, Auguste Lam, Alain Ostrovsky, Jonathan Planchot, Vincent Farys, Julien Ducoté, Marc Mikolajczak, Vincent Morin, Nicolas Chojnowski, Frank Sundermann, Alice Pelletier, Regis Bouyssou, Cedric Monget, Jean-Damien Chapon, Bastien Orlando, Laurene Babaud, Céline Lapeyre, Emek Yesilada, Anna Szucs, Jean-Christophe Michel, Latifa Desvoivres, Onintza Ros Bengoechea, Pascal Gouraud
Author Affiliations +
Abstract
Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (<0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.
© 2015 Society of Photo-Optical Instrumentation Engineers (SPIE) 1932-5150/2015/$25.00 © 2015 SPIE
Bertrand Le-Gratiet, Jean De-Caunes, Maxime Gatefait, Auguste Lam, Alain Ostrovsky, Jonathan Planchot, Vincent Farys, Julien Ducoté, Marc Mikolajczak, Vincent Morin, Nicolas Chojnowski, Frank Sundermann, Alice Pelletier, Regis Bouyssou, Cedric Monget, Jean-Damien Chapon, Bastien Orlando, Laurene Babaud, Céline Lapeyre, Emek Yesilada, Anna Szucs, Jean-Christophe Michel, Latifa Desvoivres, Onintza Ros Bengoechea, and Pascal Gouraud "Patterning critical dimension control for advanced logic nodes," Journal of Micro/Nanolithography, MEMS, and MOEMS 14(2), 021103 (10 April 2015). https://doi.org/10.1117/1.JMM.14.2.021103
Published: 10 April 2015
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CITATIONS
Cited by 2 scholarly publications.
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KEYWORDS
Semiconducting wafers

Optical lithography

Critical dimension metrology

Process control

Photomasks

Etching

Logic

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