Dr. Antonio Salerno Profile

Dr. Antonio Salerno

Project Manager at ASML Netherlands BV

SPIE Involvement:

Author

Area of Expertise:

Lithography , Metrology , Overlay

I am a Senior Applications Engineer at ASML Netherlands.

I got my Master degree in Material Science at the University of Milano-Bicocca in Italy Magna Cum Laude in March 2005. My final assignment was the base for a Journal Paper publication (Article DOI: 10.1021/jp045581j)

I started working in the semiconductors industry at STMicroelectronics Italy in 2005 as a technology development engineer. my main tasks were related to the optimization of exposure tools for extreme resolution patterning, scanner control, process development, OPC characterization, proximity matching, overlay optimization. I took part into the development of 90, 65, 45 and 32nm technology nodes for NOR, NAND and PCM flash memories. In addition, I worked on BCD-HVG processes. during the development of 32nm node I also contributed to a publication (doi: 10.1117/12.772795)

In 2008, I moved to the Netherlands to join ASML as an Applications Engineer. In the past 10 years at ASML I covered several roles.

I started as a customer support engineer focusing on supporting the customers on their production issues, performing analysis, propose action plans and coordinating with equipment support. Furthermore, I made sure that customer requirements are considered when developing new products.
I then focused on On-product overlay root cause analysis and optimization through advanced modeling. I developed methodologies for on product overlay analysis. During this period, I also worked on YieldStar metrology applications - micro diffraction based overlay.
During the past 4 years, aside of my technical contribution, I also led several projects spanning from on-product performance optimization at customers for the main aspects of the lithography process (Overlay, Imaging, Focus, Metrology and Automation) to new product development and introduction for control loops software and metrology.

Proceedings Article | 13 March 2018 Presentation + Paper

Enabling optical metrology on small 5x5um2 in-cell targets to support flexible sampling and higher order overlay and CD control for advanced logic devices nodes

Antonio Salerno, Isabel de la Fuente, Zack Hsu, Alan Tai, Hammer Chang, Elliott McNamara, Hugo Cramer, Daoping Li

Proceedings Volume 10585, 105851I (2018) https://doi.org/10.1117/12.2297356

KEYWORDS: Overlay metrology, Metrology, Logic devices, Optical metrology, Logic, Control systems, Measurement devices, Front end of line

Read Abstract +

In next generation Logic devices, overlay control requirements shrink to sub 2.5nm level on-product overlay. Historically on-product overlay has been defined by the overlay capability of after-develop in-scribe targets. However, due to design and dimension, the after development metrology targets are not completely representative for the final overlay of the device. In addition, they are confined to the scribe-lane area, which limits the sampling possibilities. To address these two issues, metrology on structures matching the device structure and which can be sampled with high density across the device is required. Conventional after-etch CDSEM techniques on logic devices present difficulties in discerning the layers of interest, potential destructive charging effects and finally, they are limited by the long measurement times[1] [2] [3] . All together, limit the sampling densities and making CDSEM less attractive for control applications. Optical metrology can overcome most of these limitations. Such measurement, however, does require repetitive structures. This requirement is not fulfilled by logic devices, as the features vary in pitch and CD over the exposure field. The solution is to use small targets, with a maximum pad size of 5x5um² , which can easily be placed in the logic cell area. These targets share the process and architecture of the device features of interest, but with a modified design that replicates as close as possible the device layout, allowing for in-device metrology for both CD and Overlay. This solution enables measuring closer to the actual product feature location and, not being limited to scribe-lanes, it opens the possibility of higher-density sampling schemes across the field. In summary, these targets become the facilitator of in-device metrology (IDM), that is, enabling the measurements both in-device Overlay and the CD parameters of interest and can deliver accurate, high-throughput, dense and after-etch measurements for Logic. Overlay improvements derived from a high-densely sampled Overlay map measured with 5x5 um² In Device Metrology (IDM) targets were investigated on a customer Logic application. In this work we present both the main design aspects of the 5x5 um² IDM targets, as well as the results on the improved Overlay performance.

Proceedings Article | 7 March 2008 Paper

Double patterning overlay and CD budget for 32 nm technology node

Umberto Iessi, Sara Loi, Antonio Salerno, Pierluigi Rigolli, Elio De Chiara, Catia Turco, Roberto Colombo, Marco Polli, Antonio Mani

Proceedings Volume 6924, 692428 (2008) https://doi.org/10.1117/12.772795

KEYWORDS: Photomasks, Overlay metrology, Semiconducting wafers, Double patterning technology, Etching, Scanners, Metrology, Optical alignment, Lithography, Optical lithography

Read Abstract +

Keywords/Phrases

Search In:

Publication Years