We explore high Numerical Aperture (NA) Extreme Ultraviolet (EUV) mask specification for logic metal layer targeting A7 node. A requirement of minimum Critical Dimension (CD) of absorber on mask is investigated by Source Mask Optimization (SMO) and wafer printing simulation for pitch 20nm logic metal pattern in a horizontal direction. The Sub-Resolution Assist Feature (SRAF) horizontal absorber line width needs to be less than 4nm (1X) to avoid being printed on wafer. A minimum absorber line end tip-to-tip is also explored as a key metrics of high NA single patterning limit in Bright-Field (BF) mask with a benefit of low-n attenuated phase-shift mask.
As semiconductor industry transitions to EUV lithography in advanced technology nodes, EUV stochastic defects play a significant role in chip yield degradation. Present yield models do not account for the stochastic-driven defects that changes by both pitches and critical dimensions (CD) in EUV lithography. In this study, a novel approach that incorporates EUV stochastics into the yield modeling, using calibrated stochastic defects from wafer data is introduced. Then a comparative analysis of yield for various EUV insertion scenarios is meticulously performed. Additionally, strategies to enhance yield in EUV lithography, including CD retargeting are proposed.
The integration of curvilinear shapes in semiconductor technology is explored. Curvilinear shapes are classified into forms using Manhattan, rectilinear, and curvilinear representations. The primary objectives of employing curvilinear shapes in Optical Proximity Correction (OPC) and mask technology are identified as error reduction and the effective representation of complex shapes. Leveraging the path optimization characteristic inherent in curvilinear shapes, their utilization was studied for semiconductor layout design. Standard cell design serves as a demonstrative example to highlight these benefits. Using the DTCO Power-Performance-Area-Cost (PPAC) assessment metric, enhancements in both electrical performance and cost efficiency are showcased, compared with designs using Manhattan shapes. We propose a step-by-step adoption strategy of curvilinear design, ranging from restrictive to partial use, and even free-form routing. In addition, we address concerns regarding data volume, outlining how curvilinear representation can effectively mitigate such issues, in OPC, mask technology and layout designs.
The identification of process bottlenecks for emerging nodes is becoming critical in early technology pathfinding. This is chiefly due to the impact of many process parameters on scaling performance. Moreover, quantifying impact of process parameters on scaling performance is of utmost importance since that will determine the ultimate patterning pitches. Edge placement error (EPE) budget is a key limiter for scaling. Previously we introduced a Machine learning based analytics framework to perform impact analysis of various process assumptions on EPE. Here, we extend this framework to forecast key limitations of EUV double patterning for 2025 nodes and beyond. Following the adoption of EUV lithography, the industry is exploring increasing the numerical aperture (NA) to enable high-NA EUV processes. We apply our simulation framework to predict key process sensitivities for controlling EPE for high-NA EUV lithography.
With increasing process complexity, quantifying impact of process parameters on scaling performance is of utmost importance. Edge placement error (EPE) budget is a key limiter for scaling. We present a Machine learning based analytics framework to perform impact analysis of various process assumptions on EPE. This would help us identify in advance the process bottlenecks for emerging nodes. For imec N3 process, one key challenge is via to buried power rail overlap which is shown to have a dependence on 15 process parameters. We first generate an exhaustive dataset of overlap EPE errors with respect to process assumptions using Monte Carlo simulation. Then a neural network model was built to model EPE error for given process parameters. Our engine ranked imec N3 litho process priorities using sensitivity analysis and identified key process bottlenecks. An impact analysis was performed to demonstrate 18% improvement in overlap edge placement error. This methodology can be used to guide the community about direction of early technology path-finding to optimize device performance.
For many years traditional 193i lithography has been extended to the next technology node by means of multi-patterning techniques. However recently such a 193i technology became challenging and expensive to push beyond the technology node for complex features that can be tackled in a simpler manner by the Extreme UltraViolet Lithography (EUVL) technology. Nowadays, EUVL is part of the high-volume manufacturing device landscape and it has reached a critical decision point where one can push further the single print on 0.33NA full field scanner or move to a EUV double patterning technology with more relaxed pitches to overcome current 0.33NA stochastic limits. In this work we have selected the 28nm pitch dense line-space (P28) as critical decision check point. We have looked at the 0.33NA EUV single print because it is more cost effective than 0.33NA EUV double patterning. In addition, we have conducted a process feasibility study as P28 in single print is close to the resolution limit of the 0.33NA EUV full field scanner. We present the process results on 28nm dense line-space patterning by using Inpria’s metal-oxide (MOx) EUV resist. We discuss the lithographic and etching process challenges by looking at resist sensitivity, unbiased line edge roughness (LER) and nano patterning failures after etching (AE), using broad band plasma (BBP) and e-beam (EB) defectivity inspection tools. To get further understanding on the P28 single patterning capability we have integrated the developed EUV MOx process in a relevant iN7 technology test vehicle by developing a full P28 metallization module with ruthenium. In such a way we were able to carry on electrical tests on metallized serpentine, fork-fork and tip-to-tip structures designed with a purpose of enabling further learning on pattern failures through electrical measurements. Finally, we conclude by showing the readiness of P28 single exposure using Inpria’s MOx process on a 0.33NA EUV full field scanner.
EUV single patterning opportunity for pitch 28nm metal design is explored. Bright field mask combined with a negative tone develop process is used to improve pattern fidelity and overall process window. imec N3 (Foundry N2 equivalent) logic PNR (place and route) designs are used to deliver optimized pupil through source mask optimization and evaluate OPC technology. DFM (Design For Manufacturing) related topics such as dummy metal insertion and design CD retarget are addressed together with critical design rules (e.g. Tip-to-Tip), to provide balanced design and patterning performance. Relevant wafer data are shown as a proof of above optimization process.
We propose the use of machine learning based analytics to simplify OPC (Optical Proximity Correction) model building process which demands concurrent optimization of more than 70 parameters as nodes shrink. We first built a deep neural network architecture to predict the RMS error, for a given set of model parameters. The neural network was trained on existing OPC model parameters and corresponding output RMS data of simulations to achieve an accurate prediction of output RMS for given set of OPC model parameters. Later, a sensitivity analysis-based methodology for recursive partitioning of OPC modelling parameters was employed to reduce the total search space of OPC model simulations. This resulted in reduction of the number of OPC model iterations performed during model tuning by orders of magnitude.
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