Dr. Axel Nackaerts Profile

Dr. Axel Nackaerts

at imec

SPIE Involvement:

Author

Publications (4)

Proceedings Article | 12 March 2008 Paper

Litho variations and their impact on the electrical yield of a 32nm node 6T SRAM cell

Staf Verhaegen, Stefan Cosemans, Mircea Dusa, Pol Marchal, Axel Nackaerts, Geert Vandenberghe, Wim Dehaene

Proceedings Volume 6925, 69250R (2008) https://doi.org/10.1117/12.773333

KEYWORDS: Transistors, Line width roughness, Critical dimension metrology, Monte Carlo methods, Double patterning technology, Optical lithography, Device simulation, Electroluminescence, Etching, Very large scale integration

Read Abstract +

Proceedings Article | 21 March 2007 Paper

Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node

Axel Nackaerts, Staf Verhaegen, Mircea Dusa, Hans Kattouw, Frank van Bilsen, Serge Biesemans, Geert Vandenberghe

Proceedings Volume 6521, 65210N (2007) https://doi.org/10.1117/12.713385

KEYWORDS: Transistors, Overlay metrology, Critical dimension metrology, Etching, Lithography, Semiconducting wafers, Statistical analysis, Instrument modeling, Logic

Read Abstract +

Proceedings Article | 24 March 2006 Paper

Compensating measured intra-wafer ring oscillator stage delay with intra-wafer exposure dose corrections

Staf Verhaegen, Axel Nackaerts, Mircea Dusa, Rene Carpaij, Geert Vandenberghe, Jo Finders

Proceedings Volume 6152, 61521Y (2006) https://doi.org/10.1117/12.659320

KEYWORDS: Oscillators, Semiconducting wafers, Etching, Critical dimension metrology, Transistors, Picosecond phenomena, Analog electronics, Digital electronics, Scanners, Annealing

Read Abstract +

Proceedings Article | 5 May 2005 Paper

Optical extensions integration for a 0.314-µm² 45-nm node 6-transistor SRAM cell

Staf Verhaegen, Axel Nackaerts, Vincent Wiaux, Eric Hendrickx, Geert Vandenberghe

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.600862

KEYWORDS: Integrated optics, Lithography, Resolution enhancement technologies, Microelectronics, Manufacturing, Printing, Scanners, Fiber optic illuminators, Lithographic illumination, Double patterning technology

Read Abstract +

A target of the 45nm node development at IMEC is to produce a working 6-transistor SRAM (6-T SRAM) cell. Here we describe the lithographic solutions for this challenge. Following the requirements of the ITRS Roadmap requires challenging k₁ values. A classical 6-transistor SRAM design is difficult to scale to lower k1 values for imaging and overlay reasons. In this paper we discuss the litho friendly design that was used to originally produce a working 0.314μm² 45nm node 6-transistor SRAM cell. The design was scaled to a k₁ value of 0.31 for printing the active area layer on a 0.75NA ArF scanner at IMEC. Later on this was further scaled to a k₁ of 0.280 and a cell size of 0.274μm² for a working cell and imaging with a k₁ of 0.265 on a higher NA tool. Various resolution enhancement techniques have been used for the three most critical layers of the SRAM cell: active area, poly gates and contact holes. Although designed unidirectional, the active area and the poly layer of the SRAM cell have critical features in two directions and therefore choosing the right illuminator shape is not straightforward. A pupil shape optimizer was used to maximize the contrast of the aerial image of the various critical features in these layers. For the contact layer the minimal pitch in the design is 160nm, which corresponds to a k₁ of 0.31. The pattern was split up into two images to increase the minimum pitch for the imaging to 190nm. Since off-axis illumination is used to print the 190nm pitch, assist features are added to the more sparse features. Contacts are not placed on a regular rectangular grid and additionally non-square contacts are used for local interconnects. This complicates the placement of the assist features and the interference mapping lithography (IML) technology was used to help in this task. The split design has been used in a double patterning approach in the SRAM process flow. In this paper we show that all the above-mentioned resolution enhancement techniques have been successfully integrated and that it resulted in a working 45nm node SRAM cell.

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years