Dr. Bob Gleason Profile

Dr. Bob Gleason

General Manager

SPIE Involvement:

Author

Publications (29)

Proceedings Article | 8 November 2012 Paper

EUV multilayer defect compensation (MDC) by absorber pattern modification: improved performance with deposited material and other progresses

Linyong Pang, Masaki Satake, Ying Li, Peter Hu, Vikram Tolani, Danping Peng, Dongxue Chen, Bob Gleason

Proceedings Volume 8522, 85220J (2012) https://doi.org/10.1117/12.977174

KEYWORDS: Carbon, Extreme ultraviolet, Double positive medium, Photomasks, Multilayers, Contamination, Transmission electron microscopy, Electroluminescence, Calibration, Refractive index

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Proceedings Article | 8 November 2012 Paper

Bridging the gaps between mask inspection/review systems and actual wafer printability using computational metrology and inspection (CMI) technologies

Linyong Pang, Vikram Tolani, Masaki Satake, Peter Hu, Danping Peng, Tingyang Liu, Dongxue Chen, Bob Gleason, Anthony Vacca

Proceedings Volume 8522, 85220Z (2012) https://doi.org/10.1117/12.977176

KEYWORDS: Photomasks, Inspection, Semiconducting wafers, Scanners, Fiber optic illuminators, Metrology, Source mask optimization, Image resolution, SRAF, Inverse optics

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Proceedings Article | 14 October 2011 Paper

Double patterning for 56 nm pitch test designs using inverse lithography

Thuc Dam, Robert Gleason, Paul Rissman, Robert Sinn

Proceedings Volume 8166, 81663Q (2011) https://doi.org/10.1117/12.900852

KEYWORDS: Photomasks, Lithography, Double patterning technology, Metals, Immersion lithography, Source mask optimization, Etching, Fiber optic illuminators, Manufacturing, SRAF

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Proceedings Article | 14 October 2011 Paper

Exploring the impact of mask making constraints on double patterning design rules

Thuc Dam, Robert Sinn, Paul Rissman, Bob Gleason

Proceedings Volume 8166, 816629 (2011) https://doi.org/10.1117/12.896963

KEYWORDS: Photomasks, Lithography, Fiber optic illuminators, Double patterning technology, Mask making, Image segmentation, Back end of line, Source mask optimization, Computational lithography, Metals

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In order to achieve an economical design-to-mask (DTM) development cycle in the low k1 domain, designers, lithographers, and mask makers needed to move away from many sequentially isolated developmental activities onto one collaborative environment managed by a computational lithography platform that integrates their respective ecosystems. ^1,2 A successful development cycle used to be achievable by designers providing designs to lithographers, who then provided RET/OPC solutions to realize designs, but once k1 fell below a certain level, the lithographers could not provide solutions to realize some critical designs, which then required feedback to designers for further redesigns requiring further lithographic evaluation cycles. So collaboration and automations between lithographers and designers became necessary to reduce feedback loops and development cycle time. RET and design solutions also were impacted by mask making, and so mask maker's feedback on MRC and other constraints needed to be integrated for all three groups to achieve an economical DTM. As many lithographers attempted to print sub-80 nm pitches with 193 nm wavelength, it became necessary to use double patterning to achieve feature resolution. With the effective pitch doubling on each split layer, there could be significant increased design rule freedom for certain complex design situations. Using an integrated computational lithographic platform, one could find design space sweet spots that could further achieve optimal lithographic performance. In this paper, the optimization of design rules (DRD) for double pattern designs (~60 nm pitch) was explored with the mask maker's perspective. The experiment to be presented started with a 2x nm design set of clips. Each set of clips underwent size/width/space/pitch variations to generate a design space, and then each design space underwent SMO with an inverse lithography technology (ILT) engine using various mask MRC's and manhattan segmentations. The lithographic results were analyzed with respect to MRC and manhattan segmentation to show their impact on design space and mask solutions.

Proceedings Article | 14 October 2011 Paper

SMO applied to contact layers at the 32nm node and below with consideration of MEEF and MRC

Te-Hung Wu, Robert Sinn, Bob Gleason, JongDoo Kim, Jiyoung Hong, Sejin Park, Sukjoo Lee

Proceedings Volume 8166, 81660V (2011) https://doi.org/10.1117/12.896503

KEYWORDS: Photomasks, Source mask optimization, Fiber optic illuminators, SRAF, Logic, Optimization (mathematics), Critical dimension metrology, Semiconducting wafers, Detection and tracking algorithms, Image segmentation

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Proceedings Article | 23 March 2011 Paper

Comparison of clear-field and dark-field images with optimized masks

Robert Sinn, Thuc Dam, Bob Gleason

Proceedings Volume 7973, 79731V (2011) https://doi.org/10.1117/12.879533

KEYWORDS: Photomasks, Optical lithography, Current controlled current source, Lithography, Opacity, Performance modeling, Phase shifts, Source mask optimization

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Proceedings Article | 23 March 2011 Paper

Enhancing fullchip ILT mask synthesis capability for IC manufacturability

Thomas Cecil, Chris Ashton, David Irby, Lan Luan, D. H. Son, Guangming Xiao, Xin Zhou, David Kim, Bob Gleason, H. J. Lee, W. J. Sim, M. J. Hong, S. G. Jung, S. S. Suh, S. W. Lee

Proceedings Volume 7973, 79731C (2011) https://doi.org/10.1117/12.882814

KEYWORDS: Photomasks, Lithography, Optical proximity correction, Manufacturing, SRAF, Image segmentation, Inverse problems, Optimization (mathematics), Electronics, Electroluminescence

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Proceedings Article | 29 September 2010 Paper

Improving model prediction accuracy for ILT with aggressive SRAFs

Sunggon Jung, Woojoo Sim, Moongyu Jeong, Junghoon Ser, Sungwoo Lee, Seoung-woon Choi, Xin Zhou, Lan Luan, Thomas Cecil, Donghwan Son, Robert Gleason, David Kim

Proceedings Volume 7823, 782311 (2010) https://doi.org/10.1117/12.864528

KEYWORDS: SRAF, Optical proximity correction, Scanning electron microscopy, Calibration, Diffusion, Photomasks, Lithography, Performance modeling, Cadmium sulfide, Critical dimension metrology

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Proceedings Article | 10 March 2010 Paper

Optimization from design rules, source and mask, to full chip with a single computational lithography framework: level-set-methods-based inverse lithography technology (ILT)

Linyong Pang, Danping Peng, Peter Hu, Dongxue Chen, Tom Cecil, Lin He, Guangming Xiao, Vikram Tolani, Thuc Dam, Ki-Ho Baik, Bob Gleason

Proceedings Volume 7640, 76400O (2010) https://doi.org/10.1117/12.848145

KEYWORDS: Source mask optimization, Photomasks, Lithography, SRAF, Optical proximity correction, Photovoltaics, Optimization (mathematics), Logic, Semiconducting wafers, Computational lithography

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Proceedings Article | 10 March 2010 Paper

Evaluation of lithographic benefits of using ILT techniques for 22nm-node

Yi Zou, Yunfei Deng, Jongwook Kye, Luigi Capodieci, Cyrus Tabery, Thuc Dam, Anthony Aadamov, Ki-Ho Baik, Linyong Pang, Bob Gleason

Proceedings Volume 7640, 76400L (2010) https://doi.org/10.1117/12.848479

KEYWORDS: Photomasks, Lithography, Source mask optimization, SRAF, Fiber optic illuminators, Metals, Optical proximity correction, Atrial fibrillation, Logic, Optimization (mathematics)

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Proceedings Article | 4 March 2010 Paper

Source-mask optimization (SMO): from theory to practice

Thuc Dam, Vikram Tolani, Peter Hu, Ki-Ho Baik, Linyong Pang, Bob Gleason, Steven Slonaker, Jacek Tyminski

Proceedings Volume 7640, 764028 (2010) https://doi.org/10.1117/12.848257

KEYWORDS: Source mask optimization, Photomasks, Photovoltaics, Fiber optic illuminators, Fluctuations and noise, Polarization, Lithography, Scanners, Optimization (mathematics), Calibration

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Proceedings Article | 12 December 2009 Paper

Source mask optimization (SMO) at full chip scale using inverse lithography technology (ILT) based on level set methods

Linyong Pang, Peter Hu, Danping Peng, Dongxue Chen, Tom Cecil, Lin He, Guangming Xiao, Vikram Tolani, Thuc Dam, Ki-Ho Baik, Bob Gleason

Proceedings Volume 7520, 75200X (2009) https://doi.org/10.1117/12.843578

KEYWORDS: Source mask optimization, Photomasks, SRAF, Lithography, Optical proximity correction, Photovoltaics, Optimization (mathematics), Logic, Semiconducting wafers, Manufacturing

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Proceedings Article | 30 September 2009 Paper

Source-mask co-optimization (SMO) using level set methods

Vikram Tolani, Peter Hu, Danping Peng, Tom Cecil, Robert Sinn, Linyong Pang, Bob Gleason

Proceedings Volume 7488, 74880Y (2009) https://doi.org/10.1117/12.833430

KEYWORDS: Photomasks, Photovoltaics, Source mask optimization, Logic, Lithography, SRAF, Mathematical modeling, Model-based design, Performance modeling, Optical proximity correction

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Proceedings Article | 9 June 2009 Paper

Trade-off between inverse lithography mask complexity and lithographic performance

Byung-Gook Kim, Sung Soo Suh, Byung-Sung Kim, Sang-Gyun Woo, Han-Ku Cho, Vikram Tolani, Grace Dai, Dave Irby, Kechang Wang, Guangming Xiao, David Kim, Ki-Ho Baik, Bob Gleason

Proceedings Volume 7379, 73791M (2009) https://doi.org/10.1117/12.824299

KEYWORDS: Photomasks, Lithography, Inspection, Logic, Manufacturing, Optical proximity correction, Model-based design, Scanning electron microscopy, Image processing, Systems modeling

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Proceedings Article | 13 March 2009 Paper

Exploration of complex metal 2D design rules using inverse lithography

Simon Chang, James Blatchford, Steve Prins, Scott Jessen, Thuc Dam, Guangming Xiao, Linyong Pang, Bob Gleason

Proceedings Volume 7275, 72750D (2009) https://doi.org/10.1117/12.814197

KEYWORDS: Metals, Lithography, Photomasks, Optical lithography, Logic, Raster graphics, Resolution enhancement technologies, Computer simulations, Distributed computing, Visualization

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As design rule (DR) scaling continues to push lithographic imaging to higher numerical aperture (NA) and smaller k1 factor, extensive use of resolution enhancement techniques becomes a general practice. Use of these techniques not only adds considerable complexity to the design rules themselves, but also can lead to undesired and/or unanticipated problematic imaging effects known as "hotspots." This is particularly common for metal layers in interconnect patterning due to the many complex random and bidirectional (2D) patterns present in typical layout. In such situations, the validation of DR becomes challenging, and the ability to analyze large numbers of 2D layouts is paramount in generating a DR set that encodes all lithographic constraints to avoid hotspot formation. Process window (PW) and mask error enhancement factor (MEEF) are the two most important lithographic constraints in defining design rules. Traditionally, characterization of PW and MEEF by simulation has been carried out using discrete cut planes. For a complex 2D pattern or a large 2D layout, this approach is intractable, as the most likely location of the PW or MEEF hotspots often cannot be predicted empirically, and the use of large numbers of cut planes to ensure all hotspots are detected leads to excessive simulation time. In this paper, we present a novel approach to analyzing fullfield PW and MEEF using the inverse lithography technology (ILT) technique, [1] in the context of restrictive design rule development for the 32nm node. Using this technique, PW and MEEF are evaluated on every pixel within a design, thereby addressing the limitations of cut-plane approach while providing a complete view of lithographic performance. In addition, we have developed an analysis technique using color bitmaps that greatly facilitates visualization of PW and MEEF hotspots anywhere in the design and at an arbitrary level of resolution. We have employed the ILT technique to explore metal patterning options and their impact on 2D design rules. We show the utility of this technique to quickly screen specific rule and process choices-including illumination condition and process bias-using large numbers of parameterized structures. We further demonstrate how this technique can be used to ascertain the full 2D impact of these choices using carefully constructed regression suites based on standard random logic cells. The results of this study demonstrate how this simulation approach can greatly improve the accuracy and quality of 2D rules, while simultaneously accelerating learning cycles in the design phase.

Proceedings Article | 17 October 2008 Paper

Considering MEEF in inverse lithography technology (ILT) and source mask optimization (SMO)

Linyong Pang, Guangming Xiao, Vikram Tolani, Peter Hu, Thomas Cecil, Thuc Dam, Ki-Ho Baik, Bob Gleason

Proceedings Volume 7122, 71221W (2008) https://doi.org/10.1117/12.803801

KEYWORDS: Photomasks, Source mask optimization, Lithography, SRAF, Logic, Semiconducting wafers, Resolution enhancement technologies, Photovoltaics, Image processing, Optical proximity correction

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Proceedings Article | 19 May 2008 Paper

Source optimization and mask design to minimize MEEF in low k1 lithography

Guangming Xiao, Tom Cecil, Lingyong Pang, Bob Gleason, John McCarty

Proceedings Volume 7028, 70280T (2008) https://doi.org/10.1117/12.793036

KEYWORDS: Photomasks, Lithography, Image processing, SRAF, Resolution enhancement technologies, Photovoltaics, Semiconducting wafers, Source mask optimization, Design for manufacturing, Manufacturing

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Proceedings Article | 19 March 2008 Paper

Validation and application of a mask model for inverse lithography

Thuc Dam, Xin Zhou, Dongxue Chen, Anthony Adamov, Danping Peng, Bob Gleason

Proceedings Volume 6925, 69251J (2008) https://doi.org/10.1117/12.773081

KEYWORDS: Finite-difference time-domain method, Calibration, Photomasks, SRAF, 3D modeling, Panoramic photography, Lithography, Image processing, Polarization, Image transmission

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Proceedings Article | 17 March 2008 Paper

Inverse lithography as a DFM tool: accelerating design rule development with model-based assist feature placement, fast optical proximity correction and lithographic hotspot detection

Steve Prins, James Blatchford, Simon Chang, Lewis Flanagin, Scott Jessen, Sean O'Brien, Guangming Xiao, Timothy Lin, Thuc Dam, Bob Gleason

Proceedings Volume 6925, 69250E (2008) https://doi.org/10.1117/12.774581

KEYWORDS: Lithography, SRAF, Photomasks, Logic, Optical proximity correction, Lithographic illumination, Printing, Critical dimension metrology, Design for manufacturing, Model-based design

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Design rule (DR) development strategies were fairly straightforward at earlier technology nodes when node-on-node scaling could be accommodated easily by reduction of λ/NA. For more advanced nodes, resolution enhancement technologies such as off-axis illumination and sub-resolution assist features have become essential for achieving full shrink entitlement, and DR restrictions must be implemented to comprehend the inherent limitations of these techniques (e.g., forbidden pitches) and the complex and unanticipated 2D interactions that arise from having a large number of random geometric patterns within the optical ambit. To date, several factors have limited the extent to which 2D simulations could be used in the DR development cycle, including exceedingly poor cycle time for optimizing OPC and SRAF placement recipes per illumination condition, prohibitively long simulation time for characterizing the lithographic process window on large 2D layouts, and difficulty in detecting marginal lithographic sites using simulations based on discrete cut planes. We demonstrate the utility of the inverse lithography technology technique [1] to address these limitations in the novel context of restrictive DR development and design for manufacturability for the 32nm node. Using this technique, the theoretically optimum OPC and SRAF treatment for each layout are quickly and automatically generated for each candidate illumination condition, thereby eliminating the need for complex correction and placement recipes. "Ideal" masks are generated to explore physical limits and subsequently "Manhattanized" in accordance with mask rules to explore realistic process limits. Lithography process window calculations are distributed across multiple compute cores, enabling rapid full-chip-level simulation. Finally, pixel-based image evaluation enables hot-spot detection at arbitrary levels of resolution, unlike the 'cut line' approach. We have employed the ILT technique to explore forbidden-pitch contact hole printing in random logic. Simulations from cells placed in random context are used to evaluate the effectiveness of restricting pitches in contact hole design rules. We demonstrate how this simulation approach may not only accelerate the design rule development cycle, but also may enable more flexibility in design by revealing overly restrictive rules, or reduce the amount of hot-spot fixing required later in the design phase by revealing where restrictions are needed.

Proceedings Article | 7 March 2008 Paper

Evaluation of inverse lithography technology for 55nm-node memory device

Byung-ug Cho, Sung-woo Ko, Jae-seung Choi, Cheol-Kyun Kim, Hyun-jo Yang, DongGyu Yim, David Kim, Bob Gleason, KiHo Baik, Ying Cui, Thuc Dam, Linyong Pang

Proceedings Volume 6924, 692438 (2008) https://doi.org/10.1117/12.772515

KEYWORDS: Photomasks, Optical proximity correction, Lithography, Manufacturing, SRAF, Scanners, Atrial fibrillation, Calibration, Optimization (mathematics), Distance measurement

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Proceedings Article | 20 October 2006 Paper

Design-based mask metrology hot spot classification and recipe making through random pattern recognition method

Ying Cui, Kiho Baik, Bob Gleason, Malahat Tavassoli

Proceedings Volume 6349, 63490O (2006) https://doi.org/10.1117/12.690988

KEYWORDS: Metrology, Cadmium, Optical proximity correction, Pattern recognition, Logic, Image classification, Critical dimension metrology, Chromium, Library classification systems, Logic devices

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Proceedings Article | 20 October 2006 Paper

Optical properties of alternating phase-shifting masks

Bob Gleason, Wen-Hao Cheng

Proceedings Volume 6349, 63491B (2006) https://doi.org/10.1117/12.686147

KEYWORDS: Photomasks, Diffraction, Etching, Silica, Polarization, Diffraction gratings, Phase measurement, Phase shifts, Finite-difference time-domain method, Manufacturing

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Proceedings Article | 20 October 2006 Paper

Deep subwavelength mask assist features and mask errors printability in high NA lithography

Wen-Hao Cheng, Mindy Lee, Vikram Tolani, Mark Nakahma, Bob Gleason

Proceedings Volume 6349, 63494W (2006) https://doi.org/10.1117/12.686378

KEYWORDS: Photomasks, SRAF, Polarization, Optical proximity correction, Finite-difference time-domain method, Inspection, Chromium, Lithography, Printing, Immersion lithography

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Proceedings Article | 1 August 2002 Paper

Lithography strategy for 65-nm node

Yan Borodovsky, Richard Schenker, Gary Allen, Edita Tejnil, David Hwang, Fu-Chang Lo, Vivek Singh, Robert Gleason, Joseph Brandenburg, Robert Bigwood

Proceedings Volume 4754, (2002) https://doi.org/10.1117/12.476916

KEYWORDS: Optical lithography, Photomasks, Optical proximity correction, Manufacturing, Inspection, Lithography, 193nm lithography, Phase shifts, Mask making, Semiconducting wafers

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Proceedings Article | 5 June 1998 Paper

100-nm CMOS gates patterned with 3 sigma below 10 nm

Hua-Yu Liu, Carlos Diaz, Chiu Chi, R. Kavari, Peng Cheng, Min Cao, Robert Gleason, Brian Doyle, Wayne Greene, G. Ray

Proceedings Volume 3331, (1998) https://doi.org/10.1117/12.309593

KEYWORDS: Transistors, Lithography, Semiconducting wafers, Etching, Photomasks, Optical lithography, Oxides, Silicon, Deep ultraviolet, Process control

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Proceedings Article | 12 February 1997 Paper

Impact of photomasks on linewidth variation

Robert Gleason, Hua-Yu Liu

Proceedings Volume 3236, (1997) https://doi.org/10.1117/12.301199

KEYWORDS: Photomasks, Optical proximity correction, Semiconducting wafers, Projection systems, Error analysis, Logic, Lithography, Transistors, Spatial frequencies, Manufacturing

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Proceedings Article | 26 May 1995 Paper

Quantifying proximity and related effects in advanced wafer processes

John Stirniman, Michael Rieger, Robert Gleason

Proceedings Volume 2440, (1995) https://doi.org/10.1117/12.209257

KEYWORDS: Semiconducting wafers, Data modeling, Critical dimension metrology, Photomasks, Wafer-level optics, Cadmium, Data processing, Lithography, Analytical research, Etching

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Proceedings Article | 26 May 1995 Paper

Contributions of stepper lenses to systematic CD errors within exposure fields

Hua-Yu Liu, Crid Yu, Robert Gleason

Proceedings Volume 2440, (1995) https://doi.org/10.1117/12.209312

KEYWORDS: Reticles, Semiconducting wafers, Error analysis, Critical dimension metrology, Manufacturing, Resistance, Lenses, Photoresist processing, Monochromatic aberrations, Diffraction

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Proceedings Article | 8 August 1993 Paper

Fabrication of 0.1-um T-shaped gates by phase-shifting optical lithography

Hua-Yu Liu, Chung-yi Su, Nigel Farrar, Robert Gleason

Proceedings Volume 1927, (1993) https://doi.org/10.1117/12.150465

KEYWORDS: Photomasks, Phase shifts, Optical lithography, Electron beam lithography, Field effect transistors, Electron beams, Polymethylmethacrylate, Metals, Optics manufacturing, Excimer lasers

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Showing 5 of 29 publications

Conference Committee Involvement (1)

Photomask Technology

1 October 2002 | Monterey, CA, United States

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