Smart pixel imaging with computational-imaging arrays (SPICA) transfers image plane coding typically realized in the optical architecture to the digital domain of the focal plane array, thereby minimizing signal-to-noise losses associated with static filters or apertures and inherent diffraction concerns. MIT Lincoln Laboratory has been developing digitalpixel focal plane array (DFPA) devices for many years. In this work, we leverage legacy designs modified with new features to realize a computational imaging array (CIA) with advanced pixel-processing capabilities. We briefly review the use of DFPAs for on-chip background removal and image plane filtering. We focus on two digital readout integrated circuits (DROICS) as CIAs for two-dimensional (2D) transient target tracking and three-dimensional (3D) transient target estimation using per-pixel coded-apertures or flutter shutters. This paper describes two DROICs – a SWIR pixelprocessing imager (SWIR-PPI) and a Visible CIA (VISCIA). SWIR-PPI is a DROIC with a 1 kHz global frame rate with a maximum per-pixel shuttering rate of 100 MHz, such that each pixel can be modulated by a time-varying, pseudorandom, and duo-binary signal (+1,-1,0). Combining per-pixel time-domain coding and processing enables 3D (x,y,t) target estimation with limited loss of spatial resolution. We evaluate structured and pseudo-random encoding strategies and employ linear inversion and non-linear inversion using total-variation minimization to estimate a 3D data cube from a single 2D temporally-encoded measurement. The VISCIA DROIC, while low-resolution, has a 6 kHz global frame rate and simultaneously encodes eight periodic or aperiodic transient target signatures at a maximum rate of 50 MHz using eight 8-bit counters. By transferring pixel-based image plane coding to the DROIC and utilizing sophisticated processing, our CIAs enable on-chip temporal super-resolution.
A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization occurs at the pixel level, enabling in-pixel DSP and noiseless data transfer from the pixel array to the peripheral processing units. The pipelined processing of row and column image data prior to off chip readout reduces the required output bandwidth of the image sensor, thus reducing the latency of computations necessary to implement various image processing systems. Data volume reductions of over 80% lead to sub 10μs latency for completing various tracking and sensor algorithms. This paper details the architecture of the pixel-processing imager (PPI) and presents some initial results from a prototype device fabricated in a standard 65nm CMOS process hybridized to a commercial off-the-shelf short-wave infrared (SWIR) detector array.
Since 2006, MIT Lincoln Laboratory has been developing Digital-pixel Focal Plane Array (DFPA) readout integrated
circuits (ROICs). To date, four 256 × 256 30 μm pitch DFPA designs with in-pixel analog to digital conversion have
been fabricated using IBM 90 nm CMOS processes. The DFPA ROICs are compatible with a wide range of detector
materials and cutoff wavelengths; HgCdTe, QWIP, and InGaAs photo-detectors with cutoff wavelengths ranging from
1.6 to 14.5 μm have been hybridized to the same digital-pixel readout. The digital-pixel readout architecture offers high
dynamic range, A/C or D/C coupled integration, and on-chip image processing with low power orthogonal transfer
operations. The newest ROIC designs support two-color operation with a single Indium bump connection.
Development and characterization of the two-color DFPA designs is presented along with applications for this new
digital readout technology.
To enable development of novel signal processing circuits, a high-speed surface-channel charge
coupled device (CCD) process has been co-integrated with the Lincoln Laboratory 180-nm RF fully depleted
silicon-on-insulator (FDSOI) CMOS technology. The CCDs support charge transfer clock speeds in excess of
1 GHz while maintaining high charge transfer efficiency (CTE). Both the CCD and CMOS gates are formed
using a single-poly process, with CCD gates isolated by a narrow phase-shift-defined gap. CTE is strongly
dependent on tight control of the gap critical dimension (CD).
In this paper we review the tradeoffs encountered in the co-integration of the CCD and CMOS
technologies. The effect of partial coherence on gap resolution and pattern fidelity is discussed. The impact of
asymmetric bias due to phase error and phase shift mask (PSM) sidewall effects is presented, along with
adopted mitigation strategies. Issues relating to CMOS pattern fidelity and CD control in the double patterning
process are also discussed.
Since some signal processing CCD structures involve two-dimensional transfer paths, many required
geometries present phase compliance and trim engineering challenges. Approaches for implementing non-compliant
geometries, such as T shapes, are described, and the impact of various techniques on electrical
performance is discussed.
KEYWORDS: Readout integrated circuits, Sensors, Staring arrays, Signal to noise ratio, Interference (communication), Analog electronics, Filtering (signal processing), Long wavelength infrared, Signal processing, CMOS technology
Although CMOS technology scaling has provided tremendous power and circuit density benefits for innumerable
applications, focal plane array (FPA) readouts have largely been left behind due to dynamic range and signal-to-noise
considerations. However, if an appropriate pixel front end can be constructed to interface with a mostly digital pixel, it
is possible to develop sensor architectures for which performance scales favorably with advancing technology nodes.
Although the front-end design must be optimized to interface with a particular detector, the dominant back end
architecture provides considerable potential for design reuse.
In this work, digitally dominated long wave infrared (LWIR) active pixel sensors with cutoff wavelengths
between 9 and 14.5 μm are demonstrated. Two ROIC designs are discussed, each fabricated in a 90-nm digital CMOS
process and implementing a 256 x 256 pixel array on a 30-μm pitch. In one of the implemented designs, the feasibility
of implementing a 15-μm pixel pitch FPA with a 500 million electron effective well depth, less than 0.5% non-linearity
in the target range and a measured NEdT of less than 50 mK at f/4 and 60 K is demonstrated. Simple on-FPA signal
processing allows for a much reduced readout bandwidth requirement with these architectures.
To demonstrate the potential for commonality that is offered by a digitally dominated architecture, this LWIR
sensor design is compared and contrasted with other digital focal plane architectures. Opportunities and challenges for
application of this approach to various detector technologies, optical wavelength ranges and systems are discussed.
Massachusetts Institute of Technology, Lincoln Laboratory (MIT LL) has been developing both continuous and burst
solid-state focal-plane-array technology for a variety of high-speed imaging applications. For continuous imaging, a
128 × 128-pixel charge coupled device (CCD) has been fabricated with multiple output ports for operating rates greater
than 10,000 frames per second with readout noise of less than 10 e- rms. An electronic shutter has been integrated into
the pixels of the back-illuminated (BI) CCD imagers that give snapshot exposure times of less than 10 ns.
For burst imaging, a 5 cm × 5 cm, 512 × 512-element, multi-frame CCD imager that collects four sequential image
frames at megahertz rates has been developed for the Los Alamos National Laboratory Dual Axis Radiographic
Hydrodynamic Test (DARHT) facility. To operate at fast frame rates with high sensitivity, the imager uses the same
electronic shutter technology as the continuously framing 128 × 128 CCD imager. The design concept and test results are
described for the burst-frame-rate imager.
Also discussed is an evolving solid-state imager technology that has interesting characteristics for creating large-format
x-ray detectors with ultra-short exposure times (100 to 300 ps). The detector will consist of CMOS readouts for high
speed sampling (tens of picoseconds transistor switching times) that are bump bonded to deep-depletion silicon
photodiodes. A 64 × 64-pixel CMOS test chip has been designed, fabricated and characterized to investigate the
feasibility of making large-format detectors with short, simultaneous exposure times.
We analyze the performance and process latitudes of a high-throughput, all-optical lithography method that addresses the requirements of the 32-nm node. This hybrid scheme involves a double exposure and only a single photomask. The first exposure forms dense gratings using maskless immersion interference lithography. These regular grating patterns are then trimmed in a second exposure with conventional projection lithography. While the highest resolution features are formed with interference imaging, the trimming operation requires significantly lower resolution. We have performed lithography simulations examining a number of representative 32-nm node patterns; both one-dimensional and two-dimensional. The results indicate that 32-nm node lithography requirements can be met using a hybrid optical maskless (HOMA) approach. Trim photomasks can be two to three generations behind the fine features, while the trim projection tools can be one to two generations behind the fine features. This hybrid optical maskless method has many of the benefits of maskless lithography without the severe throughput challenge of currently proposed maskless technologies.
The extension of optical lithography to ever deeper sub-wavelength feature sizes has led to an alarming increase in photo-mask complexity and associated cost. Changes in design philosophy can play a key role in mitigating this trend. We propose the introduction of a new optimization cycle early in the physical design process based on minimizing pattern complexity. We study the use of a pattern complexity metric based on Fourier coding to accomplish such an optimization. The ultimate goal is simplification of resolution enhancement technology (RET) methods required for a given design and the generation of a correspondingly simpler and more cost effective mask set.
The steady move towards feature sizes ever deeper in the subwavelength regime has necessitated the increased use of aggressive resolution enhancement techniques (RET) in optical lithography. The use of ever more complex RET methods including strong phase shift masks and complex OPC has led to an alarming increase in the cost of photomasks, which cannot be amortized by many types of semiconductor applications. This paper reviews an alternative RET approach, dense template phase shift lithography, that can substantially reduce the cost of optical RET. The use of simple dense grating templates can also eliminate serious problems encountered in subwavelength lithography including optical proximity and spatial frequency effects. We show that, despite additional design rule restrictions and the use of multiple exposures per critical level, this type of lithography approach can make economic sense depending on the number of wafers produced per critical photomask.
The rise of low-k1 optical lithography in integrated circuit manufacturing has introduced new questions concerning the physical and practical limits of particular subwavelength resolution-enhanced imaging approaches. For a given application, trade-offs between mask complexity, design cycle time, process latitude and process throughput must be well understood. It has recently been shown that a dense-only phase shifting mask (PSM) approach can be applied to technology nodes approaching the physical limits of strong PSM with no proximity effects. Such an approach offers the benefits of reduced mask complexity and design cycle time, at the expense of decreased process throughput and limited design flexibility. In particular, dense-only methods offer k1<0.3, thus enabling 90 nm node lithography with high-numerical aperture 248 nm exposure systems. We present the results of experiments, simulations, and analysis designed to explore the trade-offs inherent in dense-only phase shift lithography. Gate and contact patterns corresponding to various fully scaled circuits are presented, and the relationship between process complexity and design latitude is discussed. Particular attention is given to approaches for obtaining gate features in both the horizontal and vertical orientation. Since semiconductor investment is dependent on cost amortization, the applicability of these methods is also considered in terms of production volume.
Image placement errors and their effect on process latitude are a remaining issue in the development of strong phase shift mask technology. In this work, we will review the various causes of image placement error for strong phase shift imaging, including both mask and stepper lens contributions. We will also review various methods of minimizing these image shift errors including the mask fabrication process, stepper lens improvement, and proper design of the lithography process. We will also present experimental results showing how aerial image asymmetry effects can be minimized by the use of an optimized resist process.
The rise of low-k1 optical lithography in IC manufacturing has introduced new questions concerning the physical and practical limits of particular sub-wavelength resoltuion-enhanced imaging approaches. For a given application tradeoffs between mask complexity design cycle time, process latitude and process throughput must be well understood. It has recently been shown that a dense-only PSM approach can be applied to technology nodes approaching the physical limits of strong PSM with no proximity effects. Such an approach offers the benefits of reduced mask complexity and design cycle time, at the expense of decreased process throughput and limited design flexibility. In particular, dense-only methods offer k1 < 0.3, thus enabling 90-nm node lithography with high-NA 248 nm exposure systems. We presents the results of experiments, simulations, and analysis designed to explore the tradeoffs inherent in dense-only phase shift lithography. Gate and contact patterns corresponding to various fully scaled circuits are presented, and the relationship between process complexity and design latitude is discussed. Particular attention is given to approaches for obtaining gate features in both the horizontal and vertical orientation. Since semiconductor investment is dependent on cost amortization, the applicability of these methods is also considered in terms of production volume.
We present results looking into the feasibility of 100-nm Node imaging using KrF, 248-nm, exposure technology. This possibility is not currently envisioned by the 1999 ITRS Roadmap which lists 5 possible options for this 2005 Node, not including KrF. We show that double-exposure strong phase- shift, combined with two mask OPC, is capable of correcting the significant proximity effects present for 100-nm Node imaging at these low k1 factors. We also introduce a new PSM Paradigm, dubbed 'GRATEFUL,' that can image aggressive 100-nm Node features without using OPC. This is achieved by utilizing an optimized 'dense-only' imaging approach. The method also allows the re-use of a single PSM for multiple levels and designs, thus addressing the mask cost and turnaround time issues of concern in PSM technology.
Achieving CD control for sub-100 nm processes will be challenging due to the low-k1 regime that optical patterning approaches will be required to work in. New challenges are expected to arise related to new lithography tools, photoresists, reticle types, and in some cases multiple exposures per layer. This work examines the intra-field CD variations for a range of sub-100 nm resist features patterned by chromeless phase-shift 248-nm lithography. One significant advantage of this patterning technique is that the resist CD's are a function of the exposure dose. This provides the ability to examine the CD variations of a range of linewidths in a single experiment without relying on reticle pattern scaling to determine the linewidth printed on the wafer. In addition to exploring CD control vs feature size, we also examine the full-field depth of focus for these features.
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