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Since triple AIM design has 3 locations left for patterning layers insertion, a new design with 2 layers locations, location-A (inner) and location-B (middle), are generated by 1st pattering, i.e. once lithography exposure, and the 2 marks grouping are formed on dielectric through lithography and etching process with a predetermined overlay "zero offset" through original mask layout design, as illustrated in Fig. (1).
And then, as following top photo resist layer, assumed location-C (outer), lithography patterning process, PR coating, exposure and development complete, full triple-AIM patterns is generated, and 3 sets of overlay data could be obtained, A to B, C to B, C to A.
Through re-calculating the overlay raw data of current (2nd patterning layer) to previous (1st patterning layer) layer by averaging [C to B] and [C to A], then theoretically the data extraction of sites would be more accuracy, since the variation of local marks signal, induced by inline process instability, could be minimized through the raw data averaging procedure.
Moreover, from raw data [A to B], an extra monitor function for detections of the inline process variation, marks selection and recipe setting optimization could be obtained, since marks in [A] and [BB] locations are both generated in 1st patterning, and with the target "zero".
So if the raw data [A to BB] is bigger or smaller than "zero" in some degree, there should be some process issue or marks condition setting error in triple-AIM design.
Double patterning using 193nm immersion lithography has been adapted as the solution to enable 14nm technology nodes. The overlay control is one of the key figures for the successful realization of this technology. In addition to the various error contributions from the wafer scanner, the reticles play an important role in terms of considering lithographic process contributed errors. Accurate pattern placement of the features on reticles with a registration error below 4nm is mandatory to keep overall photomask contributions to overlay of sub 20nm logic within the allowed error budget.
In this paper, we show in-die registration errors using 14nm DPT product masks, by measuring in-die overlay patterns comparing with regular registration patterns. The mask measurements are used to obtain an accurate model to predict mask contribution on wafer overlay of double patterning technology.
Finally, we conclude that both imaging overlay technology and DBO-1 technology are fully successful and have a valid roadmap for the next few design nodes, with some use cases better suited for one or the other measurement technologies. Having both imaging and DBO technology options available in parallel, allows Overlay Engineers a mix and match overlay measurement strategy, providing back up when encountering difficulties with one of the technologies and benefiting from the best of both technologies for every use case.
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