KEYWORDS: Critical dimension metrology, Semiconducting wafers, Scanning electron microscopy, Inspection, Electron microscopes, Defect inspection, Data acquisition, Etching, Field effect transistors
In this paper, we tested a novel methodology of measuring critical dimension (CD) uniformity, or CDU, with electron
beam (e-beam) hotspot inspection and measurement systems developed by Hermes Microvision, Inc. (HMI). The
systems were used to take images of two-dimensional (2D) array patterns and measure CDU values in a custom
designated fashion. Because this methodology combined imaging of scanning micro scope (SEM) and CD value
averaging over a large array pattern of optical CD, or OCD, it can measure CDU of 2D arrays with high accuracy, high
repeatability and high throughput.
This paper assesses the readiness of EUV masks for pilot line production. The printability
of well characterized reticle defects, with particular emphasis on those reticle defects that
cause electrical errors on wafer test chips, is investigated. The reticles are equipped with
test marks that are inspected in a die-to-die mode (using DUV inspection tool) and
reviewed (using a SEM tool), and which also comprise electrically testable patterns. The
reticles have three modules comprising features with 32 nm ground rules in 104 nm pitch,
22 nm ground rules with 80 nm pitch, and 16 nm ground rules with 56 nm pitch (on the
wafer scale). In order to determine whether specific defects originate from the substrate,
the multilayer film, the absorber stack, or from the patterning process, the reticles were
inspected after each fabrication step. Following fabrication, the reticles were used to print
wafers on a 0.25 NA full-field ASML EUV exposure tool. The printed wafers were
inspected with state of the art bright-field and Deep UV inspection tools. It is observed
that the printability of EUV mask defects down to a pitch of 56 nm shows a trend of
increased printability as the pitch of the printed pattern gets smaller - a well established
trend at larger pitches of 80 nm and 104 nm, respectively. The sensitivity of state-of-the-art
reticle inspection tools is greatly improved over that of the previous generation of
tools. There appears to be no apparent decline in the sensitivity of these state-of-the-art
reticle inspection tools for higher density (smaller) patterns on the mask, even down to
56nm pitch (1x). Preliminary results indicate that a blank defect density of the order of
0.25 defects/cm2 can support very early learning on EUV pilot line production at the 16nm node.
Reticle defectivity was evaluated using two known approaches: direct reticle inspection and the inspection of the
wafer prints. The primary test vehicle was a reticle with a design consisting of 45 nm and 60 nm comb and
serpentine structures in different orientations. The reticle was inspected in reflected light on the KLA 587 in a die-todie
and a die-to-database mode. Wafers were exposed on a 0.25 NA full-field EUV exposure tool and inspected on a
KLA 2800. Both methods delivered two populations of defects which were correlated to identify coinciding
detections and mismatches. In addition, reticle defects were reviewed using scanning electron microscopy (SEM) to
assess the printability. Furthermore, some images of the defects found on the 45 nm reticle used in the previous
study [1] were collected using actinic (EUV) microscopy. The results of the observed mask defects are presented and
discussed together with a defect classification.
Initial characterization of the damascene process was obtained with the new coherent gradient sensing (CGS) interferometer on 200 and 300 mm wafers. The current study represents an extension of earlier work by taking advantage of the greater spatial resolution and data density of the CGS technique relative to more typical non-contact capacitance or laser scanning techniques. The comprehensiveness of the data provides insight into the uniformity of curvature and stress across the wafer. Measurements using the CGS technique were completed at multiple processing steps with principal emphasis being placed upon 300 mm dual damascene processing. It is shown that the greatest changes in wafer stress/topography occur as the wafer progresses through PVD barrier/seed, copper plate, copper anneal, and copper CMP. Of special interest in these studies is the formation of non-visual mechanical defects at a die level scale. Such measurements of valuable wafer properties are useful in not only process development, but also in process monitoring.
Non-visual defects are anomalies that result in electrical fail at final wafer test but are not detectable in-line with the current optical defect detection tool set. These defects have been found to constitute a major potion of the list of reasons for electrical yield loss. Non-visual defects may be so small they are beyond the resolution of available optical tools, they may have no physical remnant, they may be mechanical or electrical in nature, or they may be due to subtle process variations, or parametric variations. In order to understand the exact nature of the non-visual defect problem,
International SEMATECH (ISMT) conducted an industry survey of eight major semiconductor device manufacturers. The 2002 "Non-visual Defect Detection Survey" was designed to determine which specific levels, processes, and defect types are of most concern to semiconductor manufacturers for causing non-visual defects. In this paper, the major
observations, issues, and recommendations that resulted from the survey will be presented, as well as directions for future non-visual defect detection based on survey results.
Conference Committee Involvement (4)
Data Analysis and Modeling for Patterning Control III
23 February 2006 | San Jose, California, United States
Data Analysis and Modeling for Process Control II
3 March 2005 | San Jose, California, United States
Data Analysis and Modeling for Process Control
26 February 2004 | Santa Clara, California, United States
Process and Materials Characterization and Diagnostics in IC Manufacturing II
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