Ongoing research directed at integrating 1.55 μm III-V ridge waveguide gain elements (i.e. diode lasers and
semiconductor optical amplifiers) co-axially aligned with, and coupled to, silicon oxy-nitride waveguides on silicon
substrates is presented. The integration techniques used are highly modular and consistent with fabricating waveguides
on Si-CMOS wafers and doing the integration of the III-V gain elements after all standard front- and back-end Si
processing has been completed. A novel micro-cleaving technique is used to produce active ridge waveguide platelets
on the order of 6 µm thick and 100 μm wide, with precisely controlled lengths, in the current work 300 ± 1 μm, and
cleaved end facets. Typical ridge guide micro-cleaved platelet lasers have thresholds under 30 mA. Micro-cleaved
platelets are bonded within dielectric recesses etched through the oxy-nitride (SiOxNy) waveguides on a wafer so the
ridge and SiOxNy waveguides are co-axially aligned. Transmission measurements indicate coupling losses are as low as
5 db with air filling the gaps between the waveguide ends, and measurements made through filled gaps indicate that the
coupling losses can be reduced to below 1.5 dB with a high index (n = 2.2) dielectric fill. Simulations indicate that with
further optimization of the mode profile in the III-V waveguide the loss can be reduced to below 1 dB. The paper
concludes with a discussion of device design and optimization for co-axial recess integration, and with a comparison of
co-axial coupling with the hybrid evanescent vertical coupling III-V/Si integration approach recently introduced by
researchers at UCSB and Intel.
Laterial p-i-n photodiodes have been produced in a standard, unmodified commercial GaAs integrated circuit process (Vitesse Semiconductor Inc. HGaAs IV and V). The devices were modelled using the MEDICI simulation package, achieving a very good fit to both capacitance and DC light response measuremnts. The simulation recreated an interesting feature of the devices, wherein the detectors go from a low-performance to high-performance regime abruptly at a specific reverse bias. An analysis of the simulated behavior of the depletion region in the nominally intrinsic region of the device provided a partial answer to the physics behind this bias point. A second generation of devices of different geometries was fabricated and tested. The newer fabrication process showed a lower performance transition (~0.6 V) than the previous process (~4 V) for an identical layout geometry. Preliminary high-speed measurements of the newer devices are quite encouraging.
Joseph Ahadian, Steven Patterson, Praveen Vaidyanathan, Yakov Royter, Daniel Mull, Gale Petrich, William Goodhue, Sheila Prasad, Leslie Kolodziejski, Clifton Fonstad
Optical interconnects for use in high speed computing and communication systems require dense optoelectronic integrated circuits (OEICs). Monolithic integration of III-V optoelectronics with VLSI optoelectronics with VLSI- complexity electronics will yield OEICs of the high density, performance, manufacturability, and reliability. The epitaxy-on-electronics (EoE) technique monolithically integrates optoelectronic devices with commercially- fabricated, fully-metallized GaAs VLSI integrated circuits. This manuscript reviews the EoE process and details the fabrication of integrated LEDs. This LED-OEIC process is being used by optical interconnect systems researchers on a prototype basis through the OPTOCHIP project: the current status of this effort is reviewed.
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