Through the adoption of EUV lithography and an increase in numerical aperture (NA), smaller and more complex patterns can now be achieved through single exposure while significantly enhancing throughput. However, due to the variations in pattern shapes and densities, optical proximity correction (OPC) is required, leading to increased computational costs. This study aims to reduce line width variation on wafers and minimize OPC through source optimization. The process was performed under 0.33NA and 0.55NA conditions with a low-n absorbent material. The target pattern was a line and space pattern, focusing on making the same line width among various pitches. High pattern fidelity could be achieved by optimizing the source, while maintaining sufficient imaging performance.
The effect of polarized illumination in enhancing pattern fidelity and resolution in high NA EUV is examined. The influence of polarization on two key performance metrics: NILS and nDOF is systematically analyzed. As is known, polarized illumination significantly improves both metrics, leading to better resolution and the process window overall imaging performance in high NA EUV, where maintaining high resolution and image quality is particularly challenging. Integrating polarization into source optimization proves to be highly effective, expanding the process window. The importance of polarized illumination is highlighted in overcoming the resolution limits of high NA EUV lithography, making it a key enabler for future advancements in semiconductor manufacturing.
High-NA EUV lithography is essential for advanced semiconductor manufacturing, particularly for DRAM contact hole patterning. One of the primary challenges in High-NA systems is the intensity variation between the center and edges of the slit. Additionally, critical dimension differences in the x and y directions are further complicated by anamorphic optics and arc-slit illumination configurations, adding to the overall process complexity in High-NA lithography. To address these challenges, we conducted source optimization using a rigorous lithography simulation tool for contact hole patterns, with whole arc-slit configuration. This optimization, considering the full arc-slit effect, successfully reduced intensity variation across the slit. Further refinement in pattern fidelity through threshold level light intensity adjustments improved process margins for both vertical and horizontal patterns. By minimizing the need for optical proximity correction and mask bias, our approach simplifies the pattern transfer process from mask to wafer, enhancing accuracy. Additionally, source optimization combined with precise illumination control significantly improves the process window, particularly when dealing with the arc-slit configuration, facilitating the manufacturability of DRAM patterns in high NA EUV lithography.
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