ASML NXE (0.33 NA) scanners are now commonly used for High Volume Manufacturing (HVM) of 7nm and 5 nm logic devices as well as 1z memory node devices. In 2021, ASML has introduced the NXE:3600D scanner to the market, targeting 3nm logic and 1a and 1b memory nodes. This system has entered the HVM phase and is shipping in volume. In this paper we will share the latest performance, with excellent imaging, overlay and productivity results. For the latter we will show record performance of 185 Wafers per Hour at dose 30mJ/cm2 and over 3000 Wafers per Day at customer. Furthermore, we will address the ASML roadmap and introduce the NXE:3800E scanner. The NXE:3800E will first ship in the fourth quarter of 2023, targeting the 2 nm logic node. Lastly, ASML will show its carbon footprint and energy reduction roadmap.
0.33 NA EUV scanners are being used for High Volume Manufacturing. In this paper we will give an update on the performance improvements of the NXE:3400 systems related to the lithographic performance, productivity and uptime.
Finally we look at future system improvements to meet requirements for the 3 nm node and beyond.
In 2019 we have seen the first 7 nm logic devices, manufactured on ASML NXE:3400 scanners, hitting the market. In this paper we will give an update on the performance improvements to further optimize these systems for High Volume Manufacturing (HVM), related to the lithographic performance, productivity and uptime.
We will also demonstrate that for the 5 nm logic node and 10nm-class DRAM, excellent overlay, focus, and critical dimension (CD) control have been realized. In combination with intrinsic tool stability and holistic control schemes, including (resist and tool) performance improvements addressing stochastics issues, this provides the required performance for HVM for these nodes.
Finally we will discuss the ASML roadmap for meeting the requirements for the 3 nm node and beyond.
While EUV systems equipped with a 0.33 Numerical Aperture (NA) lens are readying to start high volume manufacturing, ASML and ZEISS are in parallel ramping up their activities on an EUV exposure tool with an NA of 0.55.
The purpose of this high-NA scanner, targeting an ultimate resolution of 8nm, is to extend Moore’s law throughout the next decade.
A novel lens design, capable of providing the required Numerical Aperture, has been identified; this lens will be paired with new, faster stages and more accurate sensors enabling the tight focus and overlay control needed for future process nodes.
In this paper an update will be given on the status of the developments at ZEISS and ASML. Next to this, we will address several topics inherent in the new design and smaller target resolution: M3D effects, polarization, focus control and stitching.
While EUV systems equipped with a 0.33 Numerical Aperture (NA) lens are readying to start high volume manufacturing, ASML and Zeiss are in parallel ramping up their activities on an EUV exposure tool with an NA of 0.55.
The purpose of this high-NA scanner, targeting an ultimate resolution of 8nm, is to extend Moore’s law throughout the next decade.
A novel lens design, capable of providing the required Numerical Aperture, has been identified; this lens will be paired with new, faster stages and more accurate sensors enabling the tight focus and overlay control needed for future process nodes.
In this paper an update will be given on the status of the developments at Carl Zeiss and ASML. Next to this, we will address several topics inherent in the new design and smaller target resolution: M3D effects, polarization, focus control and stitching.
While 0.33NA EUV systems are readying to start volume manufacturing, ASML and Zeiss are ramping up development activities on a 0.55NA EUV exposure tool, extending Moore’s law throughout the next decade. A novel, anamorphic lens design, has been developed to provide the NA; this lens will be paired with new, faster stages and more accurate sensors and the tight focus and overlay control needed for future process nodes. This paper presents an overview of the target specifications, key technology innovations and imaging simulations demonstrating the advantages as compared to 0.33NA and showing the capabilities of ASML’s next generation EUV systems.
While EUV systems equipped with a 0.33 Numerical Aperture lenses are readying to start volume manufacturing, ASML and Zeiss are ramping up their activities on a EUV exposure tool with Numerical Aperture of 0.55.
The purpose of this scanner, targeting an ultimate resolution of 8nm, is to extend Moore’s law throughout the next decade.
A novel, anamorphic lens design, capable of providing the required Numerical Aperture has been investigated; This lens will be paired with new, faster stages and more accurate sensors enabling Moore’s law economical requirements, as well as the tight focus and overlay control needed for future process nodes.
The tighter focus and overlay control budgets, as well as the anamorphic optics, will drive innovations in the imaging and OPC modelling.
Furthermore, advances in resist and mask technology will be required to image lithography features with less than 10nm resolution.
This paper presents an overview of the target specifications, key technology innovations and imaging simulations demonstrating the advantages as compared to 0.33NA and showing the capabilities of the next generation EUV systems.
Progressing towards the 10nm and 7nm imaging node, pattern-placement and layer-to-layer overlay requirements keep on scaling down and drives system improvements in immersion (ArFi) and dry (ArF/KrF) scanners. A series of module enhancements in the NXT platform have been introduced; among others, the scanner is equipped with exposure stages with better dynamics and thermal control. Grid accuracy improvements with respect to calibration, setup, stability, and layout dependency tighten MMO performance and enable mix and match scanner operation. The same platform improvements also benefit focus control. Improvements in detectability and reproducibility of low contrast alignment marks enhance the alignment solution window for 10nm logic processes and beyond. The system’s architecture allows dynamic use of high-order scanner optimization based on advanced actuators of projection lens and scanning stages. This enables a holistic optimization approach for the scanner, the mask, and the patterning process. Productivity scanner design modifications esp. stage speeds and optimization in metrology schemes provide lower layer costs for customers using immersion lithography as well as conventional dry technology. Imaging, overlay, focus, and productivity data is presented, that demonstrates 10nm and 7nm node litho-capability for both (immersion & dry) platforms.
ASML's NXE platform is a multi-generation TWINSCAN™ platform using an exposure wavelength of 13.5nm,
featuring a plasma source, all-reflective optics, and dual stages operating in vacuum. The NXE:3100 is the first product
of this NXE platform. With a 0.25 NA projection optics, a planned throughput of 60 wafers/hr and dedicated chuck
overlay of 4 nm, the NXE:3100 is targeted for extreme ultraviolet lithography (EUVL) implementation at 27nm halfpitch
(hp) and below. The next generation NXE tools utilize a 0.33NA lens and include off-axis illumination for high
volume manufacturing at a resolution down to 16nm hp and a targeted throughput of >100 wafers/hr. We share details
of the performance of the 0.25NA lithography products in terms of imaging, overlay, throughput, and defectivity. We
will show that we have met the required imaging performance associated with the 27nm hp node. We will also include a
summary of the EUV source development, which is a key enabler for cost-effective introduction of EUVL into highvolume
manufacturing. Finally, we will highlight some of the technical changes we introduced to enable the transition
from 27 to 22nm lithographic performance while introducing our 0.33NA Step & Scan system, the NXE:3300B.
The semiconductor industry has adopted water-based immersion technology as the mainstream high-end litho enabler
for 5x-nm and 4x-nm devices. Exposure systems with a maximum lens NA of 1.35 have been used in volume
production since 2007, and today achieve production levels of more than 3400 exposed wafers per day. Meanwhile
production of memory devices is moving to 3x-nm and to enable 38-nm printing with single exposure, a 2nd generation
1.35-NA immersion system (XT:1950Hi) is being used. Further optical extensions towards 32-nm and below are
supported by a 3rd generation immersion tool (NXT:1950i).
This paper reviews the maturity of immersion technology by analyzing productivity, robust control of imaging, overlay
and defectivity performance using the mainstream ArF immersion production systems. We will present the latest results
and improvements on robust CD control of mainstream 4x-nm memory applications. Overlay performance, including
on-product overlay control is discussed. Immersion defect performance is optimized for several resist processes and
further reduced to ensure high yield chip production even when exposing more than 15 immersion layers.
In this paper we present a methodology to investigate and optimize the CD balance between the four
features of a final 32nm lines and space pattern created by spacer pitch doubling.
Metrology (SEM and scatterometry) was optimized to measure and separate the two lines and the
two spaces of the 32nm features. In case a space unbalance emerged during the various processing
steps such as etch and deposition, this was compensated by calculating and feed-back local dose
offsets to the scanner. For the spacer process used in this study we observe 20..40% improvement in
space CDU and space balance, when applying the dose corrections.
The TWINSCAN XT:1000H extends KrF lithography to expose layers that previously required more costly ArF
lithography. These layers, including implants and metal interconnects, contain multiple, through pitch or random, 2-
dimensional (2D) features.
In this paper, we show process windows for 115 nm random via holes using conventional illumination, 110 nm dense &
isolated via holes using a soft quasar illumination shape, 95 nm trenches through pitch with an annular illumination
mode as well as the process windows for a combination of patterns representative for implant structures using a soft
annular illumination mode.
We also prove that the XT:1000H can be integrated in an existing high volume manufacturing environment: transfer of a
65 nm logic metal-1 layer from a high NA XT:1400 dry ArF scanner to the XT:1000H has been evaluated by optimizing
the illumination settings and applying advanced mask design approaches to meet requirements for exposure latitude,
depth of focus and MEEF. In addition, we show that the CD proximity matching performance between the XT:1000H
and NA 0.8 XT:850 KrF scanners can be maximized using illumination setting optimization and EFESE focus scan.
Finally, matched machine overlay performance between the XT:1000H and an XT:1900Gi ArF immersion scanner has
been evaluated.
KrF lithography is nowadays widely used for volume production spanning many device layers ranging from front-end 90nm to mid- & back-end layers in 45nm and 32nm ITRS imaging nodes. In this paper we discuss the addition of the new high-NA XT:1000H TWINSCAN(TM)scanning exposure tool to the KrF portfolio. We discuss advances in the system design and elaborate on its imaging and overlay performance. It is shown that stable tool performance supports 80nm resolution volume manufacturing. Extendibility with polarization towards sub-80nm is also addressed.
If the minimum die area is the main objective of an ASIC application, then each critical layer will have bi-directional
mask layout. Then advanced litho technology is required to print the layers with single exposure lithography. If however
yield, electrical robustness and variability have higher priority than minimum die area, than unidirectional patterning can
be a good alternative. However, then the bi-directional layout of, especially the active area- and gate-layer, must be
redesigned in an unidirectional layout (at the expense of a larger cell-area). Moreover, if a design split in two orthogonal
unidirectional layouts can be made then the so-called cut-mask technology can be used: this is a (well-known) double
patterning technology. This paper discusses three different cut-mask compatible redesigns of the gate-layer of a complex
flip-flop cell, to be used in robust, low-cost low-power CMOS-logic applications with 45 nm ground rules and 180 nm
device pitches. The analogue circuit simulator from Cadence has been used. The results obtained with ASML's
lithography simulator, "Litho Cruiser", show that cut-mask patterning gives superior CD- and end-of-line control and
enables Design Rules with less Gate-Overlap. This again gives the circuit-designer more design freedom for choosing
the transistor width. Furthermore, the cut-mask compatible layouts can even be processed with high-NA dry KrFlithography
instead of advanced single exposure ArFi lithography. The designs are compared with a reference design
which is a traditional minimum area design with bi-directional layout.
The continuing reduction of IC device dimensions puts stringent demands on the corresponding overlay performance. As part of the total overlay budget, the effects of the different process parameters need to be characterized and well understood. In a joint development program between IMEC and ASML, the robustness of different alignment strategies to process parameters has been evaluated using the ATHENA alignment system. This paper looks at both Front-end (Shallow Trench Isolation) and Back-end (W-CMP and copper dual damascene) processing. To investigate the effect of STI processing on alignment marks in Front-end processing an extensive evaluation has been performed in which both mark design and process parameters have been varied. The robustness to typical long term process variation at the STI CMP step in a production environment has also been evaluated. To improve the robustness of alignment marks in Back-end processing, new mark designs have been evaluated. These designs have been evaluated for two different processes. The first uses traditional W-CMP and sputtered aluminum. The second uses copper dual damascene, with layer stacks consisting of both conventional and low-k dielectric materials. This knowledge will be used to generate alignment strategies for future technology nodes.
Advances in wafer processing techniques and the increase of wafer size to 300 mm present new challenges to overlay performance. This paper focuses on advances n the area of process-induced alignment accuracy using the ASML ATHENA alignment system. In the experiments, process variations were deliberately increased to characterize the influence of process-tool settings on wafer alignment performance. In the STI process flow, overlays of <32 nm on marks in silicon or marks in the STI layer have been achieved. In the back-end-of-line, aluminum layers exhibit a significant shift of alignment marks and off-line metrology targets. A geometrical model of the sputter tool is used to explain the origin of this effect. Possible improvements in process corrections are indicated. For the copper dual damascene process investigated here, the dielectrics are non-absorbing. Overlays of 25 nm on marks in silicon and 29 nm on marks in the metal layer are obtained. On 300 mm wafers, a new measurement method is capable of measuring process effects to an accuracy within 6.2 (3(sigma) ). This method is used to measure resist spin effects.
To guarantee less than 45 nm product overlay required for the 130 nm IC technology node a key in lithographic tools is a sophisticated wafer alignment sensor that is able to deal with the influences of new, advanced IC processing. To prove that product overlay performance in this range is achievable, overlay results are presented that confirm the operational concept of the new ATHENA alignment sensor on various advanced processes in both front-end as well as back-end-of-line. In particular, the influences related to Chemical Mechanical Polishing (CMP) have been studied. The robustness of the system to large variations of W-CMP process parameters is highlighted. It is argued that full exploitation of the flexibility of the sensor will allow further optimization of its operation in actual production environments and that a product overlay of 35 nm is feasible.
To extend KrF lithography below the 180nm SIA design rule node in manufacturing, an advanced DUV step and scan system utilizing a lens with an NA up to 0.7 will be required to provide sufficient process latitude. Towards the SIA's 150nm design rule node, manufacturing challenges for 248nm lithography include contact hole printing, iso-dense bias control and adequate across the field CD uniformity. All will benefit from higher NA lenses. In the paper, result obtained on a PAS 5500/700B DUV Step and Scan system are presented. The system design is based on the PAS 5500/500 with a new 0.7NA Starlith lens, AERIAL II illuminator and ATHENA advanced alignment system. Imaging of dense and isolated lines at 180nm, 150nm and below as well as 180nm and 160nm contact holes is shown. In addition to imaging performance, image plane deviation, system distortion fingerprints, single-machine overlay and multiple-machine matching results are shown. Using the ATHENA alignment system, alignment reproducibility as well as overlay result on CMP wafers will be shown. It is concluded that this exposure tool is capable of delivering imaging and overlay performance required for mass production at the 150nm design rule node, with potential for R and D applications beyond.
Processes such as chemical mechanical polishing and spin coating can result in the asymmetric deformation of alignment marks. In this paper, the effects of such asymmetric mark deformations on the accuracy of the stepper alignment system are investigate. An advanced phase grating alignment system is presented which is more robust against the above mentioned process-induced alignment deviations. The potential of the new alignment system will be illustrated with result of both numerical simulations and experimental measurements. Various process modules that are known to cause mark deformations have been investigated.
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