Prof. Hei Wong Profile

Prof. Hei Wong

at City Univ of Hong Kong

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Proceedings Article | 23 May 2005 Paper

Nanoscale MOS devices: device parameter fluctuations and low-frequency noise

Hei Wong, Hiroshi Iwai, J. J. Liou

Proceedings Volume 5844, (2005) https://doi.org/10.1117/12.610124

KEYWORDS: Oxides, Transistors, Molybdenum, Resistance, Instrument modeling, Dielectrics, Semiconducting wafers, Process modeling, Field effect transistors, Statistical analysis

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It is well-known in conventional MOS transistors that the low-frequency noise or flicker noise is mainly contributed by the trapping-detrapping events in the gate oxide and the mobility fluctuation in the surface channel. In nanoscale MOS transistors, the number of trapping-detrapping events becomes less important because of the large direct tunneling current through the ultrathin gate dielectric which reduces the probability of trapping-detrapping and the level of leakage current fluctuation. Other noise sources become more significant in nanoscale devices. The source and drain resistance noises have greater impact on the drain current noise. Significant contribution of the parasitic bipolar transistor noise in ultra-short channel and channel mobility fluctuation to the channel noise are observed. The channel mobility fluctuation in nanoscale devices could be due to the local composition fluctuation of the gate dielectric material which gives rise to the permittivity fluctuation along the channel and results in gigantic channel potential fluctuation. On the other hand, the statistical variations of the device parameters across the wafer would cause the noise measurements less accurate which will be a challenge for the applicability of analytical flicker noise model as a process or device evaluation tool for nanoscale devices. Some measures for circumventing these difficulties are proposed.

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