The particle removal efficiency (PRE) of cleaning processes diminishes whenever the minimum defect size for a specific
technology node becomes smaller. For the sub-22 nm half-pitch (HP) node, it was demonstrated that exposure to high
power megasonic up to 200 W/cm2 did not damage 60 nm wide TaBN absorber lines corresponding to the 16 nm HP
node on wafer. An ammonium hydroxide mixture and megasonics removes ≥50 nm SiO2 particles with a very high PRE.
A sulfuric acid hydrogen peroxide mixture (SPM) in addition to ammonium hydroxide mixture (APM) and megasonic is
required to remove ≥28 nm SiO2 particles with a high PRE. Time-of-flight secondary ion mass spectroscopy (TOFSIMS)
studies show that the presence of O2 during a vacuum ultraviolet (VUV) (λ=172 nm) surface conditioning step will result
in both surface oxidation and Ru removal, which drastically reduce extreme ultraviolet (EUV) mask life time under
multiple cleanings. New EUV mask cleaning processes show negligible or no EUV reflectivity loss and no increase in
surface roughness after up to 15 cleaning cycles. Reviewing of defect with a high current density scanning electron
microscope (SEM) drastically reduces PRE and deforms SiO2 particles. 28 nm SiO2 particles on EUV masks age very
fast and will deform over time. Care must be taken when reviewing EUV mask defects by SEM. Potentially new
particles should be identified to calibrate short wavelength inspection tools. Based on actinic image review, 50 nm SiO2
particles on top of the EUV mask will be printed on the wafer.
Reducing mask blank and patterned mask defects is the number one challenge for extreme ultraviolet lithography. If the
industry succeeds in reducing mask blank defects at the required rate of 10X every year for the next 2-3 years to meet
high volume manufacturing defect requirements, new inspection and review tool capabilities will soon be needed to
support this goal. This paper outlines the defect inspection and review tool technical requirements and suggests
development plans to achieve pilot line readiness in 2011/12 and high volume manufacturing readiness in 2013. The
technical specifications, tooling scenarios, and development plans were produced by a SEMATECH-led technical
working group with broad industry participation from material suppliers, tool suppliers, mask houses, integrated device
manufacturers, and consortia. The paper summarizes this technical working group's assessment of existing blank and
mask inspection/review infrastructure capabilities to support pilot line introduction and outlines infrastructure
development requirements and tooling strategies to support high volume manufacturing.
Microelectronics industry leaders routinely name the cost and cycle time of mask technology and mask supply as top
critical issues. A survey was created with support from SEMATECH and administered by David Powell Consulting
to gather information about the mask industry as an objective assessment of its overall condition. The survey is
designed with the input of semiconductor company mask technologists and merchant mask suppliers. This year's
assessment is the eighth in the current series of annual reports. With ongoing industry support, the report can be used
as a baseline to gain perspective on the technical and business status of the mask and microelectronics industries.
The report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask
industry. The results will be used to guide future investments pertaining to critical path issues. This year's survey is
basically the same as the 2005 through 2008 surveys. Questions are grouped into categories: General Business
Profile Information, Data Processing, Yields and Yield Loss Mechanisms, Delivery Times, Returns, and Services.
Within each category is a multitude of questions that create a detailed profile of both the business and technical
status of the critical mask industry. This in combination with the past surveys represents a comprehensive view of
changes in the industry.
Naturally occurring sub 30 nm defects on quartz and Low Thermal Expansion Material (LTEM) substrates were characterized by using Atomic Force Microscope(AFM). Our data indicates that a majority of defects on the incoming substrate are hard defects including large, flat particles with a height less than 5 nm, tiny particles with a size of 10 nm to 30 nm SEVD and pits with a depth of about 9 nm. All the soft particles added by handling with sizes of >50 nm can be removed with a single cleaning process. At least four cleaning cycles are required to remove all of the remaining embedded particles. However, after particle removal in their initial location a shallow pit remains. Based on detailed characterization of defect and surface by AFM, we propose that these hard particles are added during the glass polishing step and therefore it is important to revisit the glass Chemical Mechanical Polishing (CMP) processes and optimize them for defect reduction. A qualitative value for particle removal efficiency (PRE) of >99% was obtained for 20 nm Poly Styrene Latex Sphere (PSL) deposited particles on surface of glass.
Microelectronics industry leaders routinely name the cost and cycle time of mask technology and mask supply as top
critical issues. A survey was created with support from SEMATECH to gather information about the mask industry as an
objective assessment of its overall condition. This year's survey data were presented in detail at BACUS and the detailed
trend analysis presented at EMLC. The survey is designed with the input of semiconductor company mask technologists
and merchant mask suppliers. This year's assessment is the seventh in the current series of annual reports. With
continued industry support, the report can be used as a baseline to gain perspective on the technical and business status
of the mask and microelectronics industries. The report will continue to serve as a valuable reference to identify the
strengths and opportunities of the mask industry. The results will be used to guide future investments on critical path
issues. This year's survey is basically the same as the surveys in 2005 through 2007. Questions are grouped into seven
categories: General Business Profile Information, Data Processing, Yields and Yield Loss, Mechanisms, Delivery Times,
Returns, and Services. (Examples are given below). Within each category is a multitude of questions that creates a
detailed profile of both the business and technical status of the critical mask industry.
Defect free masks are a critical component to enable extreme ultraviolet lithography (EUVL). It is projected EUVL will
be inserted for the 22nm hp node with a timeframe of 2012-2013 for leading IC manufacturers. To meet the goal of
defect free masks, a concerted effort is required with emphasis on mask blank development and mask infrastructure
readiness. With this in mind, SEMATECH mask program has been uniquely positioned to make important contributions
to these areas. Together with several partners, an overall strategy has been defined focused on meeting EUVL mask
requirements including setting mask standards and enabling the mask-making infrastructure. This paper will highlight
the overview of key projects and accomplishments from the mask blank development program. It is critical that
SEMATECH and its partners be ready to meet the overall pilot line defect density requirement of 0.04 defects/cm2 at
18nm defect sensitivity by the end of 2010. Although important progress has been made, much work remains to meet
these challenging goals.
The availability of defect-free mask blanks is one of the most significant challenges facing the commercialization of extreme ultraviolet lithography (EUVL). The SEMATECH Mask Blank Development Center (MBDC) was created to drive the development of EUVL mask blanks to meet the industry's needs. EUV mask defects come from two primary sources: the incoming mask substrate and defects added during multilayer deposition. For incoming defects, we have both an in-house advanced cleaning capability and an advanced in situ defect smoothing capability. This smoothing system utilizes combinations of ion beam deposition and etch to planarize any remaining incoming substrate defects. For defects added in the multilayer deposition process, we have an aggressive program to find, identify, and eliminate the defects. This paper summarizes progress in smoothing substrate defects and eliminating ever smaller multilayer-added defects. We will show the capability of our smoothing process to planarize our existing population of bump and pit type defects and discuss how quickly this can be done. We will also discuss how many defects are added by the planarization process. In addition, we will show 53 nm sensitivity defect data for multilayer-coated EUV mask blanks.
As we approach the 22nm half-pitch (hp) technology node, the industry is rapidly running out of patterning options. Of
the several lithography techniques highlighted in the International Technology Roadmap for Semiconductors (ITRS), the
leading contender for the 22nm hp insertion is extreme ultraviolet lithography (EUVL). Despite recent advances with
EUV resist and improvements in source power, achieving defect free EUV mask blank and enabling the EUV mask
infrastructure still remain critical issues. To meet the desired EUV high volume manufacturing (HVM) insertion target
date of 2013, these obstacles must be resolved on a timely bases. Many of the EUV mask related challenges remain in
the pre-competitive stage and a collaborative industry based consortia, such as SEMATECH can play an important role
to enable the EUVL landscape. SEMATECH based in Albany, NY is an international consortium representing several of
the largest manufacturers in the semiconductor market. Full members include Intel, Samsung, AMD, IBM, Panasonic,
HP, TI, UMC, CNSE (College of Nanoscience and Engineering), and Fuller Road Management. Within the
SEMATECH lithography division a major thrust is centered on enabling the EUVL ecosystem from mask development,
EUV resist development and addressing EUV manufacturability concerns. An important area of focus for the
SEMATECH mask program has been the Mask Blank Development Center (MBDC). At the MBDC key issues in EUV
blank development such as defect reduction and inspection capabilities are actively pursued together with research
partners, key suppliers and member companies. In addition the mask program continues a successful track record of
working with the mask community to manage and fund critical mask tools programs. This paper will highlight recent
status of mask projects and longer term strategic direction at the MBDC. It is important that mask technology be ready to
support pilot line development HVM by 2013. In several areas progress has been made but a continued collaborative
effort will be needed along with timely infrastructure investments to meet these challenging goals.
Microelectronics industry leaders routinely name the cost and cycle time of mask technology and mask supply as top
critical issues. A survey was created with support from SEMATECH and administered by David Powell Consulting
to gather information about the mask industry as an objective assessment of its overall condition. The survey is
designed with the input of semiconductor company mask technologists, merchant mask suppliers, and industry
equipment makers. This year's assessment is the seventh in the current series of annual reports. With ongoing
industry support, the report can be used as a baseline to gain perspective on the technical and business status of the
mask and microelectronics industries. The report will continue to serve as a valuable reference to identify the
strengths and opportunities of the mask industry. The results will be used to guide future investments pertaining to
critical path issues. This year's survey is basically the same as the 2005 through 2007 surveys. Questions are
grouped into categories: General Business Profile Information, Data Processing, Yields and Yield Loss Mechanisms,
Delivery Times, Returns, and Services. Within each category is a multitude of questions that create a detailed profile
of both the business and technical status of the critical mask industry.
Alternating Phase Shift Mask (APSM) Technology has been developed and successfully implemented for the poly gate of 65nm node Logic application at Intel. This paper discusses the optimization of the mask design rules and fabrication process in order to enable high volume manufacturability. Intel's APSM technology is based on a dual sided trenched architecture. To meet the stringent OPC requirements associated with patterning of narrow gates required for the 65nm node, Chrome width between the Zero and Pi aperture need to be minimized. Additionally, APSM lithography has an inherently low MEEF that furthermore, drives a narrower Chrome line as compared to the Binary approach. The double sided trenched structure with narrow Chrome lines are mechanically vulnerable and prone to damage when exposed to conventional mask processing steps. Therefore, new processing approaches were developed to minimize the damage to the patterned mask features. For example, cleaning processes were optimized to minimize Chrome & quartz damage while retaining the cleaning effectiveness. In addition, mask design rules were developed which ensured manufacturability. The narrow Chrome regions between the zero and Pi apertures severely restrict the tolerance for the placement of the second level resists edges with respect to the first level. UV Laser Writer based resist patterning capability, capable of providing the required Overlay tolerance, was developed, An AIMS based methodology was used to optimize the undercut and minimize the aerial image CD difference between the Zero and Pi apertures.
Photomask lifetime has become a challenge since the introduction of high volume manufacturing 193nm photolithograph. Photomask lifetime is being impacted by a broad range of environmental and process factors resulting in inorganics crystals and organic contaminants formation as well as pellicle lifetime issues. Extensive work has been published on strategies for reduction of inorganic crystals photoinduced defects formation mainly focusing on photomask clean process improvements. This paper will focus on identifying root causes for photoinduced contaminants forming within the pellicle space area as well as identify environmental factors which have the potential of impacting pellicle membrane longevity. Outgasing experiments coupled with 193nm laser exposure tests were conducted to decouple and rank reticle/pellicle storage materials as well as pellicle outgasing contributors to photoinduced defects and identify factors impacting pellicle membrance longevity. Analytical test were conducted to compare the relative levels of reticle storage materials and pellicle outgasing contaminants. Experiments aimed at quantifying the fab environment contribution to photoinduced defects formation and impact on pellicle membrane lifetime will be discussed. Environmental conditions minimizing external contributing factors impacting photomask front side photoinduced defects formation and pellicle membrance longevity will be suggested.
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