Dr. James Beach Profile

Dr. James Beach

Senior Member/Technical Staff at SEMATECH Inc

SPIE Involvement:

Author | Instructor

Proceedings Article | 5 April 2007 Paper

The coming of age of tilt CD-SEM

B. Bunday, J. Allgair, E. Solecky, C. Archie, N. Orji, J. Beach, O. Adan, R. Peltinov, M. Bar-zvi, J. Swyers

Proceedings Volume 6518, 65181S (2007) https://doi.org/10.1117/12.714214

KEYWORDS: Photoresist materials, Semiconducting wafers, Metrology, Critical dimension metrology, Scanning electron microscopy, Scanners, Lithography, Process control, Calibration

Read Abstract +

The need for 3D metrology is becoming more urgent to address critical gaps in metrology for both lithographic and etch processes. Current generation lithographic processing (ArF source, where λ=193 nm) sometimes results in photoresist lines with re-entrant profiles or T-topping, as do many etch processes. A re-entrant profile misleads top-down metrology into reading the critical dimension (CD) as too large. Recent advances in gate process technology also raise challenges to traditional top-down metrology. One such example is the FinFET, which is truly a 3D device with 3D metrology needs. The ability to measure the bottom width of a profile is crucial for process control. Recently, tilt-beam critical dimension-scanning electron microscopy (CD-SEM) applications have been developed to measure the bottom CD of such features, using the tilted-view to "see" the bottom, avoiding the feature's larger top. This is an important achievement, as the bottom of a profile is the main feature of interest in many processes. Estimation of sidewall angle (SWA) is also important. For several years, tilt-beam CD-SEM has been an available technique for this measurement, with limited adoption by the litho-metrology community. However, in this paper we will explore another method to use the tilt feature to measure average sidewall angle, based on edgewidth measurement and the assumption of basic trapezoidal profile and known height and combined with the ability to sample multiple-features. While it will not provide exact profile shape, this technique can be quite useful in providing average profile information and will definitely exhibit good throughput. Samples used will be photoresist and etched FinFET structures to measure sidewall angles. Correlations of the results to a traceable CD-atomic force microscopy (AFM) reference measurement system are provided. Conclusions will show preliminary findings of the readiness of tilt-beam CD-SEM for measuring profile and, by extension, the status of measuring 3D structures such as FinFETs, and using CD-SEM as a direct control of lithographic tooling for T-topped photoresist profiles.

Proceedings Article | 12 May 2005 Paper

Imaging study of positive and negative tone weak phase-shifted 65 nm node contacts

James Beach, John Petersen, Robert Greenway, Mark Maslow, Susan MacDonald, Lee Margolis, Gregory Hughes

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.598535

KEYWORDS: Photomasks, Lithography, Reticles, Phase shifts, Quartz, Etching, Manufacturing, Vestigial sideband modulation, Critical dimension metrology, Nanoimprint lithography

Read Abstract +

Proceedings Article | 26 June 2003 Paper

Evaluation of SCAA mask technology as a pathway to the 65-nm node

James Beach, John Petersen, Mark Maslow, David Gerold, Diane McCafferty

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485413

KEYWORDS: Photomasks, Lithography, Semiconducting wafers, Scanners, Overlay metrology, Optical proximity correction, Fiber optic illuminators, Phase shifts, Quartz, Lithographic illumination

Read Abstract +

Proceedings Article | 27 December 2002 Paper

Imaging 100-nm contacts with high-transmission attenuated phase-shift masks

James Beach, John Petersen, Benjamin Eynon, Darren Taylor, Dave Gerold, Mark Maslow

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.467763

KEYWORDS: Photomasks, Printing, Phase shifts, Scanners, Electroluminescence, Phase measurement, Lithography, Overlay metrology, Manufacturing, Image processing

Read Abstract +

Proceedings Article | 12 July 2002 Paper

Developing an integrated imaging system for the 70-nm node using high numerical aperture ArF lithography

John Petersen, James Beach, David Gerold, Mark Maslow

Proceedings Volume 4692, (2002) https://doi.org/10.1117/12.475664

KEYWORDS: Diffraction, Photomasks, Lithography, Transistors, Lithographic illumination, Nanoimprint lithography, Optical lithography, Phase shifts, Imaging systems, Fiber optic illuminators

Read Abstract +

Proceedings Article | 24 August 2001 Paper

Sumitomo resist on various BARC substrates using SVGL micrascan 193

Martha Rajaratnam, Greg Baxter, Mark Riggs, Pedro Tasaico, John Zimmerman, James Beach, P. Holland, Chris Morris, Kyle Spurlock

Proceedings Volume 4345, (2001) https://doi.org/10.1117/12.436907

KEYWORDS: Digital signal processing, Current controlled current source, Reticles, Photoresist processing, Line edge roughness, Reflection, Scanning electron microscopy, Radon, Reflectivity, Interfaces

Read Abstract +

We used the SVGL Micrascan 193 at International Sematech to evaluate four Sumitomo resists on four BARC products. The Sumitomo resists reviewed were PAR 710A35 and PAR 71835 for sense lines, PAR 710A2 and PAR 722A3 for contact holes. We evaluated isolated line performance using PAR 715A25 and PAR 710A35. The BARC products evaluated were SiON and three commercially avaialable organic systems. BARC reflectivity curves were generated for each of the BARC chemistries to determine proper BARC thicknesses. Following resist apply and bake processing, the wafers were subjected to ArF open frame exposures on an SVGL Micrascan 193. After post exposure bake and development, the energies required to clear the exposed region(E₀) were noted. Film thickness versus E₀ value was plotted to generate swing curves and resultant E_MIN and E_MAX resist thickness points. Dense line performance was evaluated with quadrapole illumination (0.7/0.1). Isolated line and contact hole performance was evaluated using 0.6NA/0.6PC illumination, with the exception of PAR 710A35, where we evaluated isolated line performance of PAR 710A35 using quadrapole illumination (0.7/0.1). All evaluations were made at a consistent point in the illumination slot and scan of a 26 x 34mm field, each field containing through focus conditions at doses varying 5% for each respective field. The dense and isolated line features were stepped through focus in fifteen 70nm steps, while the contacts were stepped eleven times in 100nm micro steps. The samples were prepared with 3.0nm of AuPd. The critical dimensions (CD) targeted were 120nm for dense lines, 120nm and lower for isolated lines, and 150nm for contact holes. Focus auto calibration and illumination uniformity calibrations were run before the actual exposure of the wafers to ensure the tool was within specifications. Wafers were exposed to determine the nominal exposure dose. Wafers for cross section SEM were exposed and broken to evaluate footing, line width and depth of focus (DOF) performance.

Proceedings Article | 23 June 2000 Paper

Characterization of UV6 photoresist stabiliztion and implant masking for exclusive implementation in 180-nm device processing

Patrick Lysaght, Billy Nguyen, Gennadi Bersuker, Joe Bennett, Tony Hare, Theodore Doros, James Beach

Proceedings Volume 3999, (2000) https://doi.org/10.1117/12.388364

KEYWORDS: Ions, Semiconducting wafers, Boron, Photomasks, Arsenic, Deep ultraviolet, Silicon, Photoresist materials, Transistors, Plasma

Read Abstract +

As design rules dip below 180 nm, DUV scanners are used at all critical levels with overlay requirements approaching 50 nm. Overlay specifications are typically 30% of critical dimension (CD), 45 nm maximum error for 150 nm geometries, but even non- critical layers at quarter micron may still require a 45 nm overlay for optimum device packing densities. The same photoresist (PR) material employed for patterning and etching thin film layers used to define device structures may also be used as an implant mask. Cost reduction efforts have prompted a detailed evaluation of the practical limits of exclusive utilization of UV6 PR for 180 nm CMOS device processing of 200 mm diameter wafers at SEMATECH. This paper addresses the characterization of UV6 PR relative to ion implant masking in order to discontinue i-line and eliminate mix-and-match lithography processing. Initially, wafers were prepared with incremental UV6 blanket thickness and processed through a range of ion implant operations prior to dry resist stripping by oxygen (0₂) plasma ashing. ThermaWave^TM optical surface roughness measurements were performed on the resultant bare silicon (Si) surface and compared with a non-implanted control sample for evidence of ion penetration and to determine the required PR mask thickness. Realization of conditions corresponding to the onset of elevated ThermaWave^TM Units (TW) established the parameters for a narrow range investigation of ion projection through UV6. Secondary Ion Mass Spectroscopy (SIMS) ion depth profiling was extensively utilized to specify the energy absorption efficiency of UV6 for each implant species; boron (¹¹B), phosphorus (³¹P), and arsenic (⁷⁵As). Residual Gas Analysis (RGA) measurements quantified the outgassing constituent elements detected during ion bombardment. This data assisted the effort to establish the optimum UV6 cure (stabilization/bake) process parameters necessary for particle free ashing. At SEMATECH, ¹¹B, represents the most penetrating (P-well, 160 keV) standard implant operation and ⁷⁵As, (P3PAPT, anti-punchthrough, 180 keV) represents the standard operation most damaging to photoresist surface topography. Wafers with patterned UV6 PR featuring isolated and dense narrow line structures were inspected with an atomic force microscope (AFM) and verified by Scanning Emission Microscopy (SEM) Based Electron Beam Induced X-ray Spectroscopy following high dose, high current As+ implant bombardment. This technique was implemented to establish the optimum O₂ plasma ashing conditions in addition to verifying the UV6 physical feature integrity. This paper identifies the evolution of UV6 PR pertaining to standard PMOS device production. Additionally, electrical data corresponding to 250 nm transistor performance is presented for the direct comparison of i-line (GCA^TM stepper) vs. UV6 (MicraScanIII^TM DUV step and scan). The results of this research enabled the exclusive implementation of UV6 PR in favor of i-line, thereby, eliminating the need for mix-and- match reticle alignments between lithography tools through the course of full flow device manufacturing.

Proceedings Article | 23 June 2000 Paper

Measuring the effects of sub-0.1-um filtration on 248-nm photoresist performance

Barry Gotlinsky, James Beach, Michael Mesawich

Proceedings Volume 3999, (2000) https://doi.org/10.1117/12.388292

KEYWORDS: Photoresist materials, Semiconducting wafers, Nitrogen, Deep ultraviolet, Particles, Polymers, Optical lithography, Contamination, Scanning electron microscopy, Tin

Read Abstract +

Proceedings Article | 2 June 2000 Paper

Clean solutions to the incoming wafer quality impact on lithography process yield limits in a dynamic copper/low-k research and development environment

Patrick Lysaght, Israel Ybarra, Harry Sax, Gaurav Gupta, Michael West, Theodore Doros, James Beach, Jim Mello

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386483

KEYWORDS: Copper, Semiconducting wafers, Particles, Contamination, Lithography, Etching, Tantalum, Optical lithography, Chemical mechanical planarization, Corrosion

Read Abstract +

The continued growth of the semiconductor manufacturing industry has been due, in large part, to improved lithographic resolution and overlay across increasingly larger chip areas. Optical lithography continues to be the mainstream technology for the industry with extensions of optical lithography being employed to support 180 nm product and process development. While the industry momentum is behind optical extensions to 130 nm, the key challenge will be maintaining an adequate and affordable process latitude (depth of focus/exposure window) necessary for 10% post-etch critical dimension (CD) control. If the full potential of optical lithography is to be exploited, the current lithographic systems can not be compromised by incoming wafer quality. Impurity specifications of novel Low-k dielectric materials, plating solutions, chemical-mechanical planarization (CMP) slurries, and chemical vapor deposition (CVD) precursors are not well understood and more stringent control measures will be required to meet defect density targets as identified in the National Technology Roadmap for Semiconductors (NTRS). This paper identifies several specific poor quality wafer issues that have been effectively addressed as a result of the introduction of a set of flexible and reliable wafer back surface clean processes developed on the SEZ Spin-Processor 203 configured for processing of 200 mm diameter wafers. Patterned wafers have been back surface etched by means of a novel spin process contamination elimination (SpCE) technique with the wafer suspended by a dynamic nitrogen (N₂) flow, device side down, via the Bernoulli effect. Figure 1 illustrates the wafer-chuck orientation within the process chamber during back side etch processing. This paper addresses a number of direct and immediate benefits to the MicraScan III^TM deep-ultraviolet (DUV) step-and-scan system at SEMATECH. These enhancements have resulted from the resolution of three significant problems: (1) back surface particle/residual contamination, (2) wafer flatness, and (3) control of contaminant materials such as copper (Cu). Data associated with the SpCE process, optimized for flatness improvement, particle removal, and Cu contamination control is presented in this paper, as it relates to excessive consumption of the usable depth of focus (UDOF) and comprehensive yield enhancement in photolithography. Additionally, data illustrating a highly effective means of eliminating copper from the wafer backside, bevel/edge, and frontside edge exclusion zone (0.5 mm - 3 mm), is presented. The data, obtained within the framework of standard and experimental copper/low-k device production at SEMATECH, quantifies the benefits of implementing the SEZ SpCE clean operation. Furthermore, this data confirms the feasibility of utilizing existing (non-copper) process equipment in conjunction with the development of copper applications by verifying the reliability and cost effectiveness of SpCE functionality.

Showing 5 of 9 publications

Course Instructor

SC679: Introduction to Microlithography: Theory, Resolution Enhancement and Future Trends

This course covers the optics of exposure tools, the chemistry of resists, and the effects of processing variables and different exposure techniques on the final relief image. Microlithography is traced from its origins to modern day, to its likely future with emphasis placed on optical extension. Different resolution enhancement techniques are described such as off-axis illumination and the use of various phase-shift masks. The chemistry of resists are detailed and are related back to their responses to different processing parameters/behaviors. Non-conventional resist processing (now starting to receive acceptance) is also described. Finally, emerging lithography technologies are discussed to outline the likely future directions of the industry.

Expand Description +

Keywords/Phrases

Search In:

Publication Years