Dr. Janko Versluijs Profile

Dr. Janko Versluijs

at imec

SPIE Involvement:

Author

Publications (18)

Proceedings Article | 28 April 2023 Poster + Paper

Poster + Paper

BEOL N2: M2 through SAxP process from MP21 to MP26: 193i SAQP vs EUV SADP

Yannick Hermans, Chen Wu, Nunzio Buccheri, Filip Schleicher, Janko Versluijs, Daniel Montero, Bappaditya Dey, Patrick Wong, Paulina Rincon-Delgadillo, Seongho Park, Zsolt Tokei, Philippe Leray, Sandip Halder

Proceedings Volume 12494, 1249414 (2023) https://doi.org/10.1117/12.2657917

KEYWORDS: Optical lithography, Semiconducting wafers, Lithography, Back end of line, Resistance, Extreme ultraviolet lithography, Etching, Critical dimension metrology

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Proceedings Article | 23 March 2018 Presentation + Paper

Presentation + Paper

Electrical comparison of iN7 EUV hybrid and EUV single patterning BEOL metal layers

Stéphane Larivière, Christopher Wilson, Bogumila Kutrzeba Kotowska, Janko Versluijs, Stefan Decoster, Ming Mao, Marleen van der Veen, Nicolas Jourdan, Zaid El-Mekki, Nancy Heylen, Els Kesters, Patrick Verdonck, Christophe Béral, Dieter Van den Heuvel, Peter De Bisschop, Joost Bekaert, Victor Blanco, Ivan Ciofi, Danny Wan, Basoene Briggs, Arindam Mallik, Eric Hendrickx, Ryoung-han Kim, Greg McIntyre, Kurt Ronse, Jürgen Bömmels, Zsolt Tőkei, Dan Mocuta

Proceedings Volume 10583, 105830U (2018) https://doi.org/10.1117/12.2299389

KEYWORDS: Extreme ultraviolet, Optical lithography, Etching, Tin, Resistance, Metals, Semiconducting wafers, Critical dimension metrology, Photomasks, Copper

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Proceedings Article | 20 March 2018 Paper

Paper

Exploration of BEOL line-space patterning options at 12 nm half-pitch and below

S. Decoster, F. Lazzarino, L. Petersen Barbosa Lima, W. Li, J. Versluijs, S. Halder, A. Mallik, G. Murdoch

Proceedings Volume 10589, 105890E (2018) https://doi.org/10.1117/12.2297183

KEYWORDS: Dielectrics, Line edge roughness, Scanning electron microscopy, Etching, Photoresist materials, Metals, Oxides

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Proceedings Article | 21 March 2016 Paper

Paper

Analyzing block placement errors in SADP patterning

Shinji Kobayashi, Soichiro Okada, Satoru Shimura, Kathleen Nafus, Carlos Fonseca, Marc Demand, Serge Biesemans, Janko Versluijs, Monique Ercken, Philippe Foubert, Shinobu Miyazaki

Proceedings Volume 9779, 97791T (2016) https://doi.org/10.1117/12.2218597

KEYWORDS: Optical lithography, Overlay metrology, Process control, Error analysis, Semiconductors, Error control coding, Wafer inspection, Inspection, Manufacturing, Semiconducting wafers, System on a chip, Etching, Device simulation, Plasma etching, Scanning electron microscopy, Tin

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Proceedings Article | 17 March 2015 Paper

Paper

A way to integrate multiple block layers for middle of line contact patterning

E. Kunnen, S. Demuynck, M. Brouri, J. Boemmels, J. Versluijs, J. Ryckaert

Proceedings Volume 9428, 94280W (2015) https://doi.org/10.1117/12.2086081

KEYWORDS: Etching, System on a chip, Tin, Optical lithography, Oxides, Lithography, Double patterning technology, Carbon, Photomasks, Semiconducting wafers

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SPIE Journal Paper | 4 September 2013

Key contributors for improvement of line width roughness, line edge roughness, and critical dimension uniformity: 15 nm half-pitch patterning with extreme ultraviolet and self-aligned double patterning

Kaidong Xu, Laurent Souriau, David Hellin, Janko Versluijs, Patrick Wong, Diziana Vangoidsenhoven, Nadia Vandenbroeck, Harold Dekkers, Xiaoping Shi, Johan Albert, Chi Lim Tan, Johan Vertommen, Bart Coenegrachts, Isabelle Orain, Yoshie Kimura, Vincent Wiaux, Werner Boullart

JM3, Vol. 12, Issue 04, 041302, (September 2013) https://doi.org/10.1117/12.10.1117/1.JMM.12.4.041302

KEYWORDS: Line width roughness, Optical lithography, Etching, Line edge roughness, Photomasks, Silicon, Extreme ultraviolet lithography, Plasma, Plasma enhanced chemical vapor deposition, Lithography

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Proceedings Article | 12 April 2013 Paper

Paper

Simulation of spacer-based SADP (Self-Aligned Double-Patterning) for 15nm half pitch

Stewart Robertson, Patrick Wong, Janko Versluijs, Vincent Wiaux

Proceedings Volume 8683, 86830Y (2013) https://doi.org/10.1117/12.2013877

KEYWORDS: Lithography, Etching, Double patterning technology, Optical lithography, Extreme ultraviolet lithography, Extreme ultraviolet, Semiconducting wafers, Ions, Design for manufacturability, Manufacturing

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Proceedings Article | 29 March 2013 Paper

Paper

15nm HP patterning with EUV and SADP: key contributors for improvement of LWR, LER, and CDU

K. Xu, L. Souriau, D. Hellin, J. Versluijs, P. Wong, D. Vangoidsenhoven, N. Vandenbroeck, H. Dekkers, X. Shi, J. Albert, C. Tan, J. Vertommen, B. Coenegrachts, I. Orain, Y. Kimura, V. Wiaux, W. Boullart

Proceedings Volume 8685, 86850C (2013) https://doi.org/10.1117/12.2011586

KEYWORDS: Line width roughness, Etching, Optical lithography, Line edge roughness, Photomasks, Extreme ultraviolet lithography, Photoresist materials, Plasma, Silicon, Lithography

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Proceedings Article | 13 March 2012 Paper

Paper

Process development using negative tone development for the dark field critical layers in a 28nm node process

Janko Versluijs, Vincent Truffert, Gayle Murdoch, Peter De Bisschop, Darko Trivkovic, Vincent Wiaux, Eddy Kunnen, Laurent Souriau, Steven Demuynck, Monique Ercken

Proceedings Volume 8326, 83260W (2012) https://doi.org/10.1117/12.916700

KEYWORDS: Source mask optimization, Optical lithography, Etching, Semiconducting wafers, Photomasks, Immersion lithography, Metals, Lithography, Lithographic illumination, Image processing

Read Abstract +

The demand for ever shrinking semiconductor devices is driving efforts to reduce pattern dimensions in semiconductor lithography. In this work, the aim is to find a single patterning litho solution for a 28nm technology node using 193nm immersion lithography. Target poly pitch is 110nm and metal1 pitch is 90nm. For this, we have introduced a range of different techniques to reach this goal. At this node, it becomes essential to include the layout itself into the optimization process. This leads to the introduction of restricted design rules, together with the co-optimization of source and mask (SMO) and the use of customized illumination modes (freeform illumination sources; Flexray^TM). Also, negative tone development (NTD) is employed to further extend the applicability of 193nm immersion lithography. Traditionally, the printing of contacts and trenches is done by using a dark field mask in combination with a positive tone resist and positive tone development. The use of negative tone development enables images reversal. This allows benefiting from the improved imaging performance when exposing with bright field masks. The same features can be printed in positive tone resists and with improved process latitudes. At the same time intermediate metal (IM) layers are used to connect the front-end and back-end-of-line, resulting in huge area benefits compared to layouts without these IM layers. The use of these IM layers will not happen for the 28nm node, but is intended to be introduced towards the 20nm node, and beyond. Nevertheless, the choice was made to use this architecture to obtain a first learning cycle on this approach. In this study, the use of negative tone development is explored, and its use for the various dark field critical layers in a 28nm node process is successfully demonstrated. In order to obtain sufficiently large process windows, structures are printed larger than the designed target CD. As a consequence, a shrink of the structures needs to be applied to obtain the target CD after etch. Different shrink approaches are compared. Final results on wafer are discussed, focusing on critical layers as IM1, IM2, Via0 and Metal1.

Proceedings Article | 8 April 2011 Paper

Paper

Patterning challenges in setting up a 16nm node 6T-SRAM device using EUV lithography

Tom Vandeweyer, Johan De Backer, Janko Versluijs, Vincent Truffert, Staf Verhaegen, Monique Ercken, Mircea Dusa

Proceedings Volume 7969, 79691K (2011) https://doi.org/10.1117/12.881690

KEYWORDS: Optical lithography, Etching, Extreme ultraviolet lithography, Optical proximity correction, Extreme ultraviolet, Lithography, Critical dimension metrology, Photomasks, Semiconducting wafers

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Proceedings Article | 23 March 2011 Paper

Paper

Spacer defined double patterning for (sub-)20nm half pitch single damascene structures

Janko Versluijs, Yong Kong Siew, Eddy Kunnen, Diziana Vangoidsenhoven, Steven Demuynck, Vincent Wiaux, Harold Dekkers, Gerald Beyer

Proceedings Volume 7973, 79731R (2011) https://doi.org/10.1117/12.881600

KEYWORDS: Etching, Double patterning technology, Semiconducting wafers, Optical lithography, Optical alignment, Line edge roughness, Carbon, Scanning electron microscopy, Line width roughness, Oxides

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SPIE Journal Paper | 1 January 2009

30-nm half-pitch metal patterning using Motif^TM critical dimension shrink technique and double patterning

Janko Versluijs, Jean-Francois de Marneffe, Danny Goossens, Tom Vandeweyer, Vincent Wiaux, Herbert Struyf, Mireille Maenhoudt, Mohand Brouri, Johan Vertommen, Jisoo Kim, Helen Zhu

JM3, Vol. 8, Issue 01, 011007, (January 2009) https://doi.org/10.1117/12.10.1117/1.3066632

KEYWORDS: Etching, Critical dimension metrology, Optical lithography, Optical proximity correction, Metals, Scanning electron microscopy, Semiconducting wafers, Photomasks, Double patterning technology, Tin

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Proceedings Article | 1 April 2008 Paper

Paper

30nm half-pitch metal patterning using Moti CD shrink technique and double patterning

Janko Versluijs, J.-F. De Marneffe, Danny Goossens, Maaike Op de Beeck, Tom Vandeweyer, Vincent Wiaux, Herbert Struyf, Mireille Maenhoudt, Mohand Brouri, Johan Vertommen, Ji Soo Kim, Helen Zhu, Reza Sadjadi

Proceedings Volume 6924, 69242C (2008) https://doi.org/10.1117/12.774139

KEYWORDS: Etching, Optical proximity correction, Optical lithography, Double patterning technology, Photomasks, Scanning electron microscopy, Semiconducting wafers, Metals, Tin, Dielectrics

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Proceedings Article | 26 March 2007 Paper

Paper

Manufacturability issues with double patterning for 50-nm half-pitch single damascene applications using RELACS shrink and corresponding OPC

Maaike Op de Beeck, Janko Versluijs, Vincent Wiaux, Tom Vandeweyer, Ivan Ciofi, Herbert Struyf, Dirk Hendrickx, Jan Van Olmen

Proceedings Volume 6520, 65200I (2007) https://doi.org/10.1117/12.713393

KEYWORDS: Etching, Optical proximity correction, Photomasks, Double patterning technology, Semiconducting wafers, Photoresist processing, Atrial fibrillation, Optical lithography, Dielectrics, Scanning electron microscopy

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Proceedings Article | 21 March 2007 Paper

Paper

A novel plasma-assisted shrink process to enlarge process windows of narrow trenches and contacts for 45-nm node applications and beyond

Maaike Op de Beeck, Janko Versluijs, Zsolt Tőkei, Steven Demuynck, J.-F. De Marneffe, Werner Boullart, Serge Vanhaelemeersch, Helen Zhu, Peter Cirigliano, Elizabeth Pavel, Reza Sadjadi, Jisoo Kim

Proceedings Volume 6519, 65190U (2007) https://doi.org/10.1117/12.713401

KEYWORDS: Etching, Lithography, 193nm lithography, Critical dimension metrology, Polymers, Photoresist materials, Scanning electron microscopy, Semiconducting wafers, Optical lithography, Scanners

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Proceedings Article | 21 March 2007 Paper

Paper

Double pattern EDA solutions for 32nm HP and beyond

George Bailey, Alexander Tritchkov, Jea-Woo Park, Le Hong, Vincent Wiaux, Eric Hendrickx, Staf Verhaegen, Peng Xie, Janko Versluijs

Proceedings Volume 6521, 65211K (2007) https://doi.org/10.1117/12.712773

KEYWORDS: Double patterning technology, Photomasks, Optical proximity correction, Optical lithography, Metals, Electronic design automation, Etching, Manufacturing, Logic, Image processing

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The fate of optical-based lithography hinges on the ability to deploy viable resolution enhancement techniques (RET). One such solution is double patterning (DP). Like the double-exposure technique, double patterning is a decomposition of the design to relax the pitch that requires dual masks, but unlike double-exposure techniques, double patterning requires an additional develop and etch step, which eliminates the resolution degradation due to the cross-coupling that occurs in the latent images of multiple exposures. This additional etch step is worth the effort for those looking for an optical extension [1]. The theoretical k₁ for a double-patterning technique of a 32nm half-pitch (HP) design for a 1.35NA 193nm imaging system is 0.44 whereas the k₁ for a single-exposure technique of this same design would be 0.22 [2], which is sub-resolution. There are other benefits to the DP technique such as the ability to add sub-resolution assist features (SRAF) in the relaxed pitch areas, the reduction of forbidden pitches, and the ability to apply mask biases and OPC without encountering mask constraints. Similarly to AltPSM and SRAF techniques one of the major barriers to widespread deployment of double patterning to random logic circuits is design compliance with split layout synthesis requirements [3]. Successful implementation of DP requires the evolution and adoption of design restrictions by specifically tailored design rules. The deployment of double patterning does spawn a couple of issues that would need addressing before proceeding into a production environment. As with any dual-mask RET application, there are the classical overlay requirements between the two exposure steps and there are the complexities of decomposing the designs to minimize the stitching but to maximize the depth of focus (DoF). In addition, the location of the design stitching would require careful consideration. For example, a stitch in a field region or wider lines is preferred over a transistor region or narrower lines. The EDA industry will be consulted for these sound automated solutions to resolve double-patterning sensitivities and to go beyond this with the coupling of their model-based and process-window applications. This work documented the resolution limitations of single exposure, and double-patterning with the latest hyper-NA immersion tools and with fully optimized source conditions. It demonstrated the best known methods to improve design decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. These EDA solutions were further analyzed and quantified utilizing a verification flow.

Proceedings Article | 15 March 2006 Paper

Paper

Early learning on hyper-NA lithography using two-beam immersion interference

Eric Hendrickx, Maaike Op de Beeck, Roel Gronheid, Janko Versluijs, Lieve Van Look, Monique Ercken, Geert Vandenberghe

Proceedings Volume 6154, 61541X (2006) https://doi.org/10.1117/12.659007

KEYWORDS: Polarization, Liquids, Semiconducting wafers, Electroluminescence, Printing, Water, Prisms, Refractive index, Nanoimprint lithography, Scanners

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Proceedings Article | 12 May 2005 Paper

Paper

Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm

M. Maenhoudt, J. Versluijs, H. Struyf, J. Van Olmen, M. Van Hove

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.613326

KEYWORDS: Etching, Overlay metrology, Double patterning technology, Semiconducting wafers, Oxides, Resistance, Copper, Critical dimension metrology, 193nm lithography, Nanoimprint lithography

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Showing 5 of 18 publications

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