Ms. Ji Li Profile

Ji Li

at Synopsys Inc

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Author

Publications (5)

Proceedings Article | 10 April 2024 Presentation

Advancing the curvilinear ILT and OPC ecosystem for low-k1 DUV and EUV lithography

Guangming Xiao, Kevin Hooker, Yunqiang Zhang, Ji Li, Thuc Dam, Yu-Po Tang, Linghui Wu, WooJoo Sim, Kevin Lucas

Proceedings Volume 12954, 1295413 (2024) https://doi.org/10.1117/12.3014637

KEYWORDS: Photomasks, Deep ultraviolet, Optical proximity correction, Extreme ultraviolet lithography, Ecosystems, Lithography, Extreme ultraviolet, Yield improvement, Source mask optimization, Printing

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Proceedings Article | 26 May 2022 Presentation + Paper

Mask synthesis for silicon photonics devices

Rainer Zimmermann, Luis Orbe, Bernd Küchler, Ji Li, Jim Burdorf, William Stanton, Tung-Yu Su, Remco Stoffer, Ulrich Klostermann, Wolfgang Demmerle

Proceedings Volume 12148, 1214809 (2022) https://doi.org/10.1117/12.2620724

KEYWORDS: Optical proximity correction, Photomasks, Waveguides, Photonic devices, Lithography, Line edge roughness, Stochastic processes, Photonics, Signal to noise ratio

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Proceedings Article | 10 March 2010 Paper

Process window and integration results for full-chip model-based assist-feature placement at the 32 nm node and below

Ji Li, Gerard Luk-Pat, Amyn Poonawala, Kevin Lucas, Ben Painter

Proceedings Volume 7640, 76401W (2010) https://doi.org/10.1117/12.848443

KEYWORDS: Atrial fibrillation, Optical proximity correction, Photomasks, Model-based design, Cadmium sulfide, Critical dimension metrology, Manufacturing, Printing, 3D modeling, Solids

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Proceedings Article | 17 October 2008 Paper

32nm design rule and process exploration flow

Yunqiang Zhang, Jonathan Cobb, Amy Yang, Ji Li, Kevin Lucas, Satyendra Sethi

Proceedings Volume 7122, 71223Z (2008) https://doi.org/10.1117/12.801593

KEYWORDS: Optical proximity correction, Atrial fibrillation, Lithography, Lithographic illumination, Manufacturing, Resolution enhancement technologies, Optical lithography, Process modeling, Semiconductors, Semiconducting wafers

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Proceedings Article | 4 March 2008 Paper

Application of layout DOE in RET flow

Yunqiang Zhang, Paul van Adrichem, Ji Li, Amy Yang, Kevin Lucas

Proceedings Volume 6925, 69251H (2008) https://doi.org/10.1117/12.773059

KEYWORDS: Optical proximity correction, Diffractive optical elements, Atrial fibrillation, Critical dimension metrology, Resolution enhancement technologies, Lithography, Error analysis, Head, Bridges, Process modeling

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At low k1 lithography and strong off-axis illumination, it is very hard to achieve edge-placement tolerances and 2-D image fidelity requirements for some layout configurations. Quite often these layouts are within simple design rules constraint for a given technology node. Evidently it is important to have these layouts included during early RET flow development. Simple shrinkage from previous technology node is quite common, although often not enough. For logic designs, it is hard to control design styles. Moreover for engineers in fabless design groups, it is difficult to assess the manufacturability of their layouts because of the lack of understanding of the litho process. Assist features (AF) are frequently placed according to pre-determined rules to improve lithography process window. These rules are usually derived from lithographic models. Direct validation of AF rules is required at development phase.To ensure good printability through process window, process aware optical proximity correction (OPC) recipes were developed. Generally rules based correction is performed before model based correction. Furthermore, there are also lots of other options and parameters in OPC recipes for an advanced technology, thus making it difficult to holistically optimize performance of recipe bearing all these variables in mind. In this paper we demonstrate the application of layout DOE in RET flow development. Layout pattern libraries are generated using the Synopsys Test Pattern Generator (STPG), which is embedded in a layout tool (ICWB). Assessment gauges are generated together with patterns for quick correction accuracy assessment. OPC verification through full process is also deployed. Several groups of test pattern libraries for different applications are developed, ranging from simple 1D pattern for process capability study and settings of process aware parameters to a full set of patterns for the assessment of rules based correction, line end and corner interaction, active and poly interaction, and critical patterns for contact coverage, etc. Restrictive design rules (RDR) are commonly deployed to eliminate problematic layouts. We demonstrate RDR evaluation and validation using our layout design of experiments (DOE) approach. This technique of layout DOE also offers a simple and yet effective way to verify AF placement rules. For a given nominal layout features all possible assist features are generated within the mask rules constraint using STPG. Then we run OPC correction and assess main feature critical dimension (CD) at best and worst process condition in ICWB. Best assist feature placement rules are derived based on minimum CD difference. The rules derived from this approach are not the same as those derived from the commonly used method of least intensity variation.

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