High NA scanners with adjustable polarization are becoming commercially available. Linear polarization has been shown to significantly improve imaging performance of preferentially oriented lines. Azimuthal and tangential polarization are now becoming commercially available. The latter has less asymmetry in its imaging and can resolve critical features oriented in multiple directions at the same time. Linear y-oriented or vertical polarization was used, since at the time of this work, azimuthal and tangential polarization were not available. Such x- and y-oriented linear polarization could be used in double exposure imaging, for example. Just as for unpolarized imaging, OPC models are required for polarized imaging that are accurate in (a) fitting and predicting experimental CD values, (b) fragmenting layout, and (c) correcting the fragmented layout to target. This paper describes the results of such a first OPC verification loop. Experimental proximity data in X- and Y-orientation were measured. Source polarization and wafer stack thin film effects were included in the empirically fit OPC simulation model. A parallel investigation was undertaken using an unpolarized source. It served as the reference case. Simple test patterns as well product-like 2D layout was treated with the vertically polarized and unpolarized OPC models. A test mask was written and wafer printing results obtained. They demonstrated the validity of the approach and pointed to further OPC model improvements.
Lately, "Design for Manufacturability" (DFM) can be found in almost any self-respecting EDA vendor's top-five list of most critical and urgent strategic topics. While the envisioned DFM activities cover a broad spectrum of topics, the exact definition of DFM continues to evade capture [1]. However, it appears self-evident that an important portion of DFM hinges upon the availability of models accurately describing the pattern transfer from the layout to the wafer, here called "pattern transfer models" (PTMs). In combination with a suitable design environment, PTMs will allow physical designers to optimize their layout, thus ensuring the structural integrity over the process window upon transfer to the wafer. In this paper, we argue that PTMs have an importance comparable to that of the "electrical device models" (EDMs) widely used for circuit simulation. We point out some striking analogies between PTMs and EDMs, as far as the basic concepts and use models are concerned. Furthermore, we highlight the significant differences in the EDA land-scapes for both model types, most importantly the fact that an industry standard only exists for EDMs. Based on the consequences for EDA vendors and users, as well as manufacturing cooperations that derive from this situation, we formulate the call for an industry standard for PTMs for usage in "Optical Proximity Correction" (OPC) and DFM.
The annotation of electrical information or constraints is a well established method to transfer information on design intent from the electrical to the physical designer. In this paper, we will discuss the possibility to extend the concept of annotation as vehicle to hand over critical information from the physical designer to the resolution enhancement technique (RET) engineer. Opportunities and implications to extend the existing optical proximity correction (OPC) methods from the current stage of "just print the layout on wafer" towards new approaches where the layout can be optimized during the RET/OPC step based on designers input are discussed. In addition, the benefit of using process variation information for this layout optimization will be compared to a conventional OPC approach that just tries to realize an overlapping process window at one point of the process window. The power of a combination of both approaches will be shown, based on a small test case. The target of this work is to motivate further research and development in this direction to enhance the current OPC/RET capabilities towards a more integrated solution enabling annotated layout optimization as link between design and manufacturing.
Sophisticated designs of the pupil illumination fill of scanners and steppers permit considerable improvements of the resolution and the quality of the optical projection for certain critical patterns. However, the mask layout can have quite different requirements for the resolution as well as the shape of the critical patterns in the two spatial directions. For instance, typical DRAM designs have one orientation with much higher requirements than the other orientation.
This asymmetry can be accounted for with a corresponding pupil fill that has a reduced symmetry as well. It is for example possible to combine high resolution and high contrast of the most critical pattern in one spatial orientation at the cost of the other orientation. Unfortunately, this leads to an asymmetric source distribution with x-y dependent optical proximity effects. Therefore the transfer of one and the same pattern from the mask to the wafer will differ if this pattern is rotated by 90 degrees. But fortunately, this anisotropic mapping can be compensated by applying an appropriate optical proximity correction (OPC) which is anisotropic as well. In the current work, we measure on silicon the orientation dependent proximity effect for a customized and strongly asymmetric pupil illumination fill design. With this input data, we build a lithography simulation model which is able to reproduce this anisotropy well. We further perform full chip anisotropic OPC and present the actual success of this resolution enhancement technique with various measurement results and printed wafer images. We also discuss the challenges and problems of this method.
For state of the art technologies, rule based optical proximity correction (OPC) together with conventional illumination is commonly used for contact layers, because it is simple to handle and processing times are short. However, as geometries are getting smaller it becomes more difficult to accurately control critical dimension (CD) variations influenced by nearby pattern. This applies in particular for irregularly arranged contact holes. Here simulation based OPC is more effective. We present a procedure for application of simulation based OPC for a 193 nm lithography contact hole layer with rectangular contact holes of different sizes in different proximities, using attenuated phase shift masks. In order to further improve the accuracy of the simulation based OPC process, characteristics of the mask, like mask corner rounding are incorporated in the OPC process. We build an OPC model, use it for OPC processing of DRAM design data and investigate the process window of the printing contacts. The results show an overlapping process window for length and width of isolated and dense small contact holes of different length and width, which is sufficient for volume production.
In DRAM technology, rapidly decreasing critical dimensions cause a strong need in lithography for optimization of illumination conditions. In critical line levels, this will lead to an increasing demand for application of different, specially optimized illuminations to differently structured layout portions. Such a strategy can be achieved by double exposure techniques. A major technical challenge in this approach is the case in which electrically connected layout regions are assigned to different litho illuminations. Here, the layout separation onto different masks must preserve a sufficient process window in the electrically connected layout cut regions. A key success factor is a double exposure aware OPC strategy, able to describe and correct layouts defined by the interaction of two exposures with different illumination settings. In our contribution, we present the results of a double exposure experiment for a critical metal level. A likewise mask-manufacturing-friendly and litho-friendly method of layout separation on 'double tri-tone masks' was developed. Mask and wafer results show the principal feasibility of the chosen concept and prove the necessary OPC functionality.
A chrome-less phase-shift mask for the 70nm technology was designed and manufactured. The mask contains “lines and spaces” including programmed defects. Each defect was characterized with respect to the critical dimension (CD) variation on wafer, defect size, aerial image deviation, as well as inspection capture rate. It was found that defects with an AIMS intensity deviation of above 9 % are to be considered critical. The corresponding critical defect size is dependent on the defect type. All lithographically significant mask defects were found reliably using a KLA 576 inspection tool.
Recently, "design for manufacturability" (DFM) has become a veritable buzzword in the semiconductor manufacturing community. DFM activities cover a broad spectrum ranging from the improvement of the electrical and structural robustness against process variations to the reduction of layout parts critical for statistically distributed defects or sensitive to systematic process weaknesses. In our work we focus only on those aspects of DFM concerned with the structural integrity of patterns on the wafer. We show that a purely geometrical analysis of product layouts offers a powerful tool to strengthen the link between design and manufacturing. It allows, for instance, a visualisation of the extent to which intra- and inter-layer design rules determine the geometry configurations dominating the layout and the identification of patterns occurring only rarely. Furthermore, in combination with the geometry-resolved information about the accuracy of "optical proximity correction" (OPC) models and "critical dimension" (CD) control, such an analysis provides valuable input for systematic improvements on both, the product layout and manufacturing process side. In this sense it supports the progress towards making real designs still manufacturable at the limits of process tool capabilities.
Contact layers of the DRAM manufacturing process can be printed well using alternating phase-shifting masks. State-of-the-art mask making tools have sufficient performance to manufacture defect free contact masks. The enlarged process window compared to conventional masks allows to shrink the contacts size or to substitute advanced scanners by older generation steppers for contact layer patterning. Using older generation exposure systems may cause problems originating in worse lens aberration performance. A method will be described how to overcome overlay problems by applying a specifically designed OL measurement target.
The lithographic potential of various mask types for the printing of 65nm features has been investigated by simulation and experimentation. As key parameters process window, mask error enhancement factor, balancing performance, and phase and CD error susceptibility have been analyzed. Alternating chromeless phase-shifting masks (PSM) show the smallest mask error enhancement factor (MEEF), but the largest phase and CD error sensitivity. Alternating PSM have a larger MEEF but require less tight mask specifications. Double edge chromeless PSM combine small MEEF value with relaxed phase and CD control specifications when an appropriate illumination is chosen. Good intra-field CD control and sufficient large process window for 65nm pattern can be obtained for this mask type. The impact of aberrations and pupil imperfections on the CD control has been investigated. The mask processes will be discussed and mask performance data introduced.
In times of continuing aggressive shrinking of chip layouts a thorough understanding of the pattern transfer process from layout to silicon is indispensable. We analyzed the most prominent effects limiting the control of this process for a contact layer like process, printing 140nm features of variable length and different proximity using 248nm lithography. Deviations of the photo mask from the ideal layout, in particular mask off-target and corner rounding have been identified as clearly contributing to the printing behavior. In the next step, these deviations from ideal behavior have been incorporated into the optical proximity correction (OPC) modeling process. The degree of accuracy for describing experimental data by simulation, using an OPC model modified in that manner could be increased significantly. Further improvement in modeling the optical imaging process could be accomplished by taking into account lens aberrations of the exposure tool. This suggests a high potential to improve OPC by considering the effects mentioned, delivering a significant contribution to extending the application of OPC techniques beyond current limits.
The paper describes the advantages of optical proximity correction (OPC) based on defocus data instead of best focus data. By additionally acepting asymmetric variations of the dimension of different patterns e.g. for an isolated line that can become wider than its nominal width this method can deliver structures much more robust against opens and shorts than in the standard OPC approach which is based on data taken at best process conditions. The differences of both OPC methods are compared based on simulations and checked against experimental data of characteristic IC patterns.
The lithographic potential of alternating PSM for sub-100nm gate patterning have been evaluated in comparison to alternative techniques. The status of the key elements of the full level alternating PSM approach including design conversion, optical proximity correction, mask making, double exposure and phase-shifting mask imaging will be demonstrated for a 256MDRAM device. Experimental data describing the phase-shifting mask quality, the lithographic process windows and the CD control obtained for alternating PSM in full level and array only approach will be presented.
A study to partition a gate level design into an alternating phase shift mask and a chrome on glass trim mask is presented. After determination of important rules for the partitioning by simulation, all investigated gate level pattern could be partitioned, only with slight modifications of the wiring. By application of optical proximity correction (OPC) good gate width and sufficient pattern fidelity control was obtained with the chosen OPC methodology using a calibrated optical model. Nevertheless, several indications of weak spots at two dimensional patterns at extreme defocus are discussed based on experimental data and simulation. To further improve the process window of such pattern, new methods are necessary to detect and prevent such remaining weak spots.
By approaching the physical resolution limits of optical lithography for a given wavelength, data complexity on certain layers of chip layouts increases, while feature sizes decrease. This becomes even more apparent when introducing optical enhancement techniques. At the same time, more and more complex procedures to fracture mask data out of a DRC clean chip-GDS2 require checks on mask data regarding integrity, as well as mask manufacturability and inspectability. To avoid expensive redesigns and large mask house cycle times it is important to find shortcomings before the data are submitted to the mask house. As an approach to the situation depicted, a (Mask) Manufacturing Rule Check (MRC) can be introduced. Aggressive Optical Proximity Correction (OPC) is a special challenge for mask making. Recently, special algorithms for mask inspection of OPC assist features have been implemented by equipment vendors. Structures smaller than two inspection pixels, like assist structures, can be successfully inspected with certain algorithms. The impact of those algorithms on mask pattern requirements and suitable MRC adoptions will be discussed in the present paper.
We present a new method of sidelobe suppressor placement based on fast lithographic simulation. Experimental results of printing 0.18 micron contact holes using a 5.5 percent transmittance attenuated phase shift mask with different settings of partial coherency are shown. Very asymmetric side lobes appear in some of these results. To explain these experimental results simulations were performed that take koma lens aberrations into account. A good agreement between experiment and simulation can be obtained them, Using these simulations a new algorithm has been implemented to place absorbing assist pattern for sidelobe suppression suitable in size and position. Then the process window of a double contact was determined using aerial image simulation. Process windows with koma lens aberrations and different settings of the partial coherency are then compared.
Simulation-based optical proximity correction (OPC) is applied to print the gate level of a state-of-the-art, high- volume DRAM technology. Using 248 nm lithography, critical structures down to 170nm are printed.
A novel technique of sidelobe suppression based on absorbing assist pattern is introduced. Chrome shields are placed exactly at the position, where sidelobes appear. The effectiveness of this technique for sidelobe control is demonstrated by simulation and experimental results. The resulting process window enlargement for 180 nm contacts is investigated. Corresponding mask making issues are discussed.
Alternating Phase Shift Masks (alt.PSM) became one of the primary options to keep optical lithography on its fast shrinking path. They promise -- and demonstrated by numerous examples -- lithography with k1 factors down to 0.25, which is equivalent to print structures below 100 nm using established DUV exposure tools. However, lithography at that small k1 factors is a highly non-linear process. So proximity effects are expected, when realistic chip structures have to be printed. In addition to the well-known proximity effects at the use of conventional chromium masks or half-tone phase shift masks, the width of a line printed by an alt.PSM depends also on the geometry of the surrounding phase shifters. The paper confirms, that a simulation-based OPC-tool is able to describe this effect correctly and to correct for it. However, experimental data and simulation results suggest, that there is an additional proximity effect arising from the 3- dimensional geometry of the phase edges. This proximity effect changes the effective phase of a given phase edge from its intended value. It is possible to correct this effect for one geometry, but for arbitrary geometries, phase changes as function of the proximity of phase edges must be taken into account. Based on simulation results of 3-dimensional alt.PSM geometries, we developed a strategy to include all proximity effects of alt.PSM in order to print realistic chip layouts with design rules down to 130 nm.
The paper describes the extension of optical proximity correction (OPC), which is well established for conventional chromium-on-glass mask printing, to alternating phase shift masks (altPSM). Aerial image simulation of various situations of light-field and dark-field altPSM shows that the size of the phase shifter has a great impact on the printed critical dimension (CD). Especially layouts containing non-symmetric phase shifters or shifter sizes comparable to the nominal CD do not print on target. The application of optical proximity correction to the chromium structures between the phase shifters is capable to compensate for such effects. We demonstrate the added value of OPC using a simulation-based software tool for altPSM.
The pattern transfer process from the chip layout data to the structures on the finished wafer consists of many process steps. Although desired, none of these steps is linear in all aspects of the pattern transfer. Approaching the process limits due to the ever-shrinking linewidth, the non- linearities of the pattern transfer clearly show up. This means, that one cannot continue the practice to summarize all process influences into one bias between the data used for mask making and the final chip structure. The correction of process non-linearities is a necessity. This correction is usually called optical proximity correction (OPC), although not all effects intended for correction are of optical origin and/or not all these are effects of the neighborhood. We therefore propose to use the term PPC (process proximity correction). This paper reports our experiences with the application of OPTISSIMO, a software tool developed to perform automatically OPC/PPC for full chip designs. First, we provide a definition of PPC, which in our view has to correct all non- linearities of the pattern transfer process from layout data to the final electrically measured structures. Then, the strategy of the OPC/PPC tool OPTISSIMO, a software package to perform PPC based on process simulation, is discussed. We focus on the data handling strategy and on the process modeling of the tool under evaluation. It is shown, that full chip OPC/PPC is practicable using a well-designed hierarchy management system combined with a pattern library. Finally, it is demonstrated, that a model-based OPC/PPC tool is by definition a process simulation tool, that is able to perform all simulation tasks (like defect printability) at reasonable accuracy.
The point when optical proximity correction (OPC) will become a routine procedure for every design is not far away. For such a daily use the requirements for an OPC tool go far beyond the principal functionality of OPC that was proven by a number of approaches and is documented well in literature. In this paper we first discuss the requirements for a productive OPC tool. Against these requirements a benchmarking was performed with three different OPC tools available on market (OPRX from TVT, OPTISSIMO from aiss and PROTEUS from TMA). Each of these tools uses a different approach to perform the correction (rules, simulation or model). To assess the accuracy of the correction, a test chip was fabricated, which contains corrections done by each software tool. The advantages and weakness of the several solutions are discussed.
KEYWORDS: Photomasks, Head, Semiconducting wafers, Atomic force microscopy, Reticles, Deep ultraviolet, OLE for process control, Data corrections, Critical dimension metrology, Lithography
Increasing number of patterns per area and decreasing linewidth demand enhancement technologies for optical lithography. OPC, the correction of systematic non-linearity in the pattern transfer process by correction of design data is one possibility to tighten process control and to increase the lifetime of existing lithographic equipment. The two most prominent proximity effects to be corrected by OPC are CD variation and line shortening. Line shortening measured on a wafer is up to 2 times larger than full resist simulation results. Therefore, the influence of mask geometry to line shortening is a key item to parameterize lithography. The following paper discusses the effect of adding small serifs to line ends with 0.25 micrometer ground-rule design. For reticles produced on an ALTA 3000 with standard wet etch process, the corner rounding on them mask can be reduced by adding serifs of a certain size. The corner rounding was measured and the effect on line shortening on the wafer is determined. This was investigated by resist measurements on wafer, aerial image plus resist simulation and aerial image measurements on the AIMS microscope.
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