One of the key steps in the pattern formation chain of extreme ultraviolet (EUV) lithography is the development process to resolve the resist pattern after EUV exposure. A simple traditional development process might be insufficient to clear the holes in contact-hole (CH) patterns and often causes missing hole defects around target-CD. In prior papers, a new development method named ESPERT™ (Enhanced Sensitivity develoPER Technology™) has been introduced to improve the performance of metal oxide-resists (MOR) for line/space (L/S) and pillar patterns. ESPERT™ as a chemical super resolution technique effectively apodized the MOR chemical image, improving chemical gradient and reducing scums. In this work, this development technique was optimised for CH patterns to reduce both the local CD uniformity (LCDU) and to reduce the levels of missing contact holes at a lower exposure dose. This is made possible thanks to the capability of the updated version of ESPERT™ that can effectively remove the scums (resist residues) inside CH to extend the missing hole defect margins. The high development contrast of the new development technique results also in a much higher exposure latitude. Using 0.33 NA EUV scanners on 36-nmpitch hexagonal patterns, the new development enhanced exposure latitude (EL), failure free latitude (FFL), and failure free dose ranges at both ADI (after development inspection) and AEI (after etch inspection) for two diverse types of MORs. For instance, in the case of the reference MOR developed by ESPERT™, CHs were nicely transferred to a TiN layer, even for small CD holes of 14.7 nm. If compared to the data by conventional development, using the new method, the EL was increased from 16.0% to 49.1%, the FFL was extended from 2 nm to 6 nm, and the failure free dose range was increased from 13.3% to 72.2%. It was also possible to have EUV dose-to-size (DtS) of 28 mJ/cm² with EL of 49.9% at ADI, using the new development. With all those advantages, this new development method is expected to be the solution for CH pattern formation of negative tone MORs in EUV lithography.
Selective plasma etching among different dielectric materials is crucial to the manufacturing of advanced logic and memory devices. For instance, in self-aligned contact (SAC) etching, achieving highly selective SiO2 etching over Si3N4 is essential. By contrast, in self-aligned multi-patterning (SAMP), selective Si3N4 spacer removal over SiO2 and Si is necessary. To effectively control the relative etch rates of various dielectric materials, etch gas chemistry optimization [for instance, see J. Vac. Sci. Technol. A 36, 040601 (2018), J. Vac. Sci. Technol. A 34, 041307 (2016)., J. Vac. Sci. Technol. A 35, 01A102 (2017), etc.] has been extensively investigated. On the other hand, hardware capabilities such as direct current superposition (DCS) and must also be considered for their effects on plasma physics and plasma-surface interactions. In this study, we examine the etch behavior for various dielectric materials e.g. SiO2, Si3N4, and low-k dielectrics in a TEL dual-frequency CCP chamber. Specifically, we focus on the gas ratio and DCS effects in a CF4/H2/Ar plasma. Contrary to the monotonically decreasing etch rates for SiO2 and low-k vs. increasing H2/CF4 flow ratio in accordance with decreasing F/CFx density ratio, the experimental blanket Si3N4 etch rate exhibits a local maximum at H2/(CF4+H2) = 15%. Chamber-scale plasma simulations using the Hybrid Plasma Equipment Model (HPEM) indicate that the HF density is peaked at almost the same gas ratio. In addition, atomistic molecular dynamics (MD) and density functional theory (DFT) simulations reveal hydrogen’s role in modifying the Si3N4 surface through N-H bond formation, thereby creating a hydrophilic surface on which HF adsorption is enhanced. Finally, computed reactant flux trends also demonstrate that the effect of DC superposition (DCS) on the relative orders of various ion and neutral reactant fluxes to the wafer is significantly weaker compared to that of the H2/(CF4+H2) flow ratio. This suggests that the application of DCS aimed at differential charging mitigation is not expected to induce major changes in inherent material etch selectivity. These fundamental learnings provide insights to guide process development and optimization for common dielectric etch applications.
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