Mr. Ken Hanafusa Profile

Ken Hanafusa

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Proceedings Article | 23 March 2020 Presentation + Paper

Advanced memory cell design optimization with inverse lithography technology

Jiro Higuchi, Weiting Wang, Takamasa Takaki, Hiromitsu Mashita, Shigeki Nojima, Ahmed Omran, Ken Hanafusa, Seunghee Baek, Ryan Chen, Yukio Asaka, Kyle Braam, Hironobu Taoka, Guangming Xiao

Proceedings Volume 11328, 1132806 (2020) https://doi.org/10.1117/12.2557847

KEYWORDS: Photomasks, Lithography, Optical proximity correction, Bridges, Data analysis, Semiconducting wafers, Resolution enhancement technologies, SRAF

Read Abstract +

Memory cells and access structures consume a large percentage of area in embedded devices so there is a high return from shrinking the cell area as much as possible. This aggressive scaling leads to very difficult resolution, 2D CD control and process window requirements. As the scaling drives lithography even deeper into the low-k1 regime, cooptimization of design layout, mask, and lithography is critical to deliver a production-worthy patterning solution. Computational lithography like Inverse Lithography Technology (ILT) has demonstrated it is an enabling technology to derive improved solutions over traditional OPC as reported in multiple prior publications. In this paper, we will present results of a study on advanced memory cell design optimization with Cell-Level ILT (CL-ILT) where significant design hierarchy can be retained during ILT optimization. Large numbers of cell design variations are explored with automatically generated patterns from ProteusTM Test Pattern Generator (TPG). Fully automated flows from pattern generation to mask synthesis with ILT, data analysis and results visualization are built on ProteusTM Work Flow (PWF) for exploring a fully parameterized design space of interest. Mask complexity including assist features (AF) types, rule or model based, and main feature segmentation are also studied to understand the impact on wafer lithographic performance. A heatmap view of results generated from this design exploration provides a clear and intuitive way to identify maximum design limits of memory cells. Comparison of results from ILT and traditional OPC will be presented as well with both wafer and simulation data.

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