Initial readiness of extreme ultraviolet (EUV) patterning has been demonstrated at the 7-nm device node with the focus now shifting to driving the “effective” k1 factor and enabling the second generation of EUV patterning. In current EUV lithography, photoresist thicknesses <30 nm are required to meet resolution targets and mitigate pattern collapse. Etch budgets necessitate the reduction of underlayer thickness as well. Typical spin-on underlayers show high defectivity when reducing thickness to match thinner resist. Inorganic deposited underlayers are lower in defectivity and can potentially enable ultrathin EUV patterning stacks. However, poor resist-inorganic underlayer adhesion severely limits their use. Existing adhesion promotion techniques are found to be either ineffective or negatively affect the etch budget. Using a grafted polymer brush adhesion layer, we demonstrate an ultrathin EUV patterning stack comprised of inorganic underlayer, polymer brush, and resist. We show printing of sub-36-nm pitch features with a good lithography process window and low defectivity on various inorganic substrates, with significant improvement over existing adhesion promotion techniques. We systematically study the effect of brush composition, molecular weight, and deposition time/temperature to optimize grafting and adhesion. We also show process feasibility and extendibility through pattern transfer from the resist into typical back end stacks.
In this study, the integrity and the benefits of the DSA shrink process were verified through a via-chain test structure, which was fabricated by either DSA or baseline litho/etch process for via layer formation while metal layer processes remain the same. The nearest distance between the vias in this test structure is below 60nm, therefore, the following process components were included: 1) lamella-forming BCP for forming self-aligned via (SAV), 2) EUV printed guiding pattern, and 3) PS-philic sidewall. The local CDU (LCDU) of minor axis was improved by 30% after DSA shrink process. We compared two DSA Via shrink processes and a DSA_Control process, in which guiding patterns (GP) were directly transferred to the bottom OPL without DSA shrink. The DSA_Control apparently resulted in larger CD, thus, showed much higher open current and shorted the dense via chains. The non-optimized DSA shrink process showed much broader current distribution than the improved DSA shrink process, which we attributed to distortion and dislocation of the vias and ineffective SAV. Furthermore, preliminary defectivity study of our latest DSA process showed that the primary defect mode is likely to be etch-related. The challenges, strategies applied to improve local CD uniformity and electrical current distribution, and potential adjustments were also discussed.
The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.
Initial readiness of EUV patterning has been demonstrated at the 7-nm device node with the focus now shifting to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. In current EUV lithography, photoresist thicknesses <30 nm are required to meet resolution targets and mitigate pattern collapse. Etch budgets necessitate the reduction of underlayer thickness as well. Typical spin-on underlayers show high defectivity when reducing thickness to match thinner resist. Inorganic deposited underlayers are lower in defectivity and can potentially enable ultrathin EUV patterning stacks. However, poor resist-inorganic underlayer adhesion severely limits their use. Existing adhesion promotion techniques are found to be either ineffective or negatively affect the etch budget. Here, using a grafted polymer brush adhesion layer we demonstrate an ultrathin EUV patterning stack comprised of inorganic underlayer, polymer brush and resist. We show printing of sub-36 nm pitch features with good lithography process window and low defectivity on various inorganic substrates, with significant improvement over existing adhesion promotion techniques. We systematically study the effect of brush composition, molecular weight and deposition time/temperature to optimize grafting and adhesion. We also show process feasibility and extendibility through pattern transfer from the resist into typical back end stacks.
We report a systematic study of the feasibility of using directed self-assembly (DSA) in real product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design technology co-optimization (DTCO) methodology and two test cases applying both line/space type and via/cut type DSA processes. We cover the parts of DSA process flow and critical design constructs as well as a full chip capable computational lithography framework for DSA. By co-optimizing all process flow and product design constructs in a holistic way using a computational DTCO flow, we point out the feasibility of manufacturing using DSA in an advanced FinFET technology node and highlight the issues in the whole DSA ecosystem before we insert DSA into manufacturing.
Directed self-assembly (DSA) of block copolymers (BCPs) has become a promising patterning technique for 7nm node hole shrink process due to its material-controlled CD uniformity and process simplicity.[1] For such application, cylinder-forming BCP system has been extensively investigated compared to its counterpart, lamella-forming system, mainly because cylindrical BCPs will form multiple vias in non-circular guiding patterns (GPs), which is considered to be closer to technological needs.[2-5] This technological need to generate multiple DSA domains in a bar-shape GP originated from the resolution limit of lithography, i.e. those vias placed too close to each other will merge and short the circuit. In practice, multiple patterning and self-aligned via (SAV) processes have been implemented in semiconductor manufacturing to address this resolution issue.[6] The former approach separates one pattern layer with unresolvable dense features into several layers with resolvable features, while the latter approach simply utilizes the superposition of via bars and the pre-defined metal trench patterns in a thin hard mask layer to resolve individual vias, as illustrated in Fig 1 (upper). With proper design, using DSA to generate via bars with the SAV process could provide another approach to address the resolution issue.
In recent years major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCP). DSA is now widely regarded as a leading complementary patterning technique for future node integrated circuit (IC) device manufacturing and is considered for the 7 nm node. One of the most straightforward approaches for implementation of DSA is via patterning by graphoepitaxy. In this approach, the guiding pattern dictates the location and pitch of the resulting hole structures while the material properties of the BCP control the feature size and uniformity. Tight pitches need to be available for a successful implementation of DSA for future node via patterning which requires DSA in small guiding pattern CDs. Here, we show strategies how to enable the desired CD shrink in these small guiding pattern vias by utilizing high χ block copolymers and/or controlling the surface properties of the template, i.e. sidewall and bottom affinity to the blocks.
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